Infineon Technologies TC1796 - Page 1109

TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-120 V2.0, 2007-07
Regs, V2.0
DMU_
OMASK8
DMU Overlay Mask
Register 8
F801 0188
H
U, SV SV 0FFF FE00
H
DMU_
RABR9
DMU Redirected Address
Base Register 9
F801 018C
H
U, SV SV 0000 0000
H
DMU_
OTAR9
DMU Overlay Target
Address Register 9
F801 0190
H
U, SV SV 0000 0000
H
DMU_
OMASK9
DMU Overlay Mask
Register 9
F801 0194
H
U, SV SV 0FFF FE00
H
DMU_
RABR10
DMU Redirected Address
Base Register 10
F801 0198
H
U, SV SV 0000 0000
H
DMU_
OTAR10
DMU Overlay Target
Address Register 10
F801 019C
H
U, SV SV 0000 0000
H
DMU_
OMASK10
DMU Overlay Mask
Register 10
F801 01A0
H
U, SV SV 0FFF FE00
H
DMU_
RABR11
DMU Redirected Address
Base Register 11
F801 01A4
H
U, SV SV 0000 0000
H
DMU_
OTAR11
DMU Overlay Target
Address Register 11
F801 01A8
H
U, SV SV 0000 0000
H
DMU_
OMASK11
DMU Overlay Mask
Register 11
F801 01AC
H
U, SV SV 0FFF FE00
H
DMU_
RABR12
DMU Redirected Address
Base Register 12
F801 01B0
H
U, SV SV 0000 0000
H
DMU_
OTAR12
DMU Overlay Target
Address Register 12
F801 01B4
H
U, SV SV 0000 0000
H
DMU_
OMASK12
DMU Overlay Mask
Register 12
F801 01B8
H
U, SV SV 0FFF FE00
H
DMU_
RABR13
DMU Redirected Address
Base Register 13
F801 01BC
H
U, SV SV 0000 0000
H
DMU_
OTAR13
DMU Overlay Target
Address Register 13
F801 01C0
H
U, SV SV 0000 0000
H
DMU_
OMASK13
DMU Overlay Mask
Register 13
F801 01C4
H
U, SV SV 0FFF FE00
H
Table 18-37 Address Map of DMU (cont’d)
Short Name Description Address Access Mode Reset Value
Read Write