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Infineon Technologies TC1796 User Manual

Infineon Technologies TC1796
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TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-43 V2.0, 2007-07
MultiCAN, V2.0
Allocation Case 1
In this allocation case, bit field MCR.MPSEL = 0000
B
(see Page 22-66). The location
selection consists of 2 parts:
The upper three bits of MOINPRn.MPN (MPN[7:5]) select the number k of a Message
Pending Register MSPNDk in which the pending bit will be set.
The lower five bits of MOINPRn.MPN (MPN[4:0]) select the bit position (0-31) in
MSPNDk for the pending bit to be set.
Allocation Case 2
In this allocation case, bit field MCR.MPSEL is taken into account for pending bit
allocation. Bit field MCR.MPSEL makes it possible to include the interrupt request node
pointer for reception (MOIPRn.RXINP) or transmission (MOIPRn.TXINP) for pending bit
allocation in such a way that different target locations for the pending bits are used in
receive and transmit case. If MPSEL = 1111
B
, the location selection operates in the
following way:
At a transmit event, the upper 3 bits of TXINP determine the number k of a Message
Pending Register MSPNDk in which the pending bit will be set. At a receive event,
the upper 3 bits of RXINP determine the number k.
The bit position (0-31) in MSPNDk for the pending bit to be set is selected by the
lowest bit of TXINP or RXINP (selects between low and high half-word of MSPNDk)
and the four least significant bits of MPN.
General Hints
The Message Pending Registers MSPNDk can be written by software. Bits that are
written with 1 are left unchanged, and bits which are written with 0 are cleared. This
makes it possible to clear individual MSPNDk bits with a single register write access.
Therefore, access conflicts are avoided when the MultiCAN module (hardware) sets
another pending bit at the same time when software writes to the register.
Each Message Pending Register MSPNDk is associated with a Message Index Register
MSIDk (see Page 22-71) which indicates the lowest bit position of all set (1) bits in
Message Pending Register k. The MSIDk register is a read-only register that is updated
immediately when a value in the corresponding Message Pending Register k is changed
by software or hardware.

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Infineon Technologies TC1796 Specifications

General IconGeneral
BrandInfineon Technologies
ModelTC1796
CategoryController
LanguageEnglish