TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual 3-13 V2.0, 2007-07
Clock, V2.0
N-Divider
The N-Divider in the feedback path of the PLL divides the VCO clock f
VCO
by factor N for
the N-divider output clock f
N
. This feedback clock is used as input clock for the PLL
phase detection unit, which compares it with the PLL input clock f
P
. The phase detector
determines the difference between its two input clocks f
P
and f
N
and accordingly
regulates the frequency of the VCO output clock f
VCO
.
Table 3-3 shows the N factor values of the N-Divider which are selected by
programming the PLL_CLC.NDIV bit field. It also lists the resulting N-divider output clock
f
N
depending on N and dedicated VCO frequencies. Note that the N-Divider factor is
always PLL_CLC.NDIV+1. For proper operation of the PLL, only N-Divider values of 20
to 100 are allowed.
Table 3-3 N-Divider Selections
PLL_CLC.
NDIV
1)
1) These columns include decimal values.
N-Divider:
N=NDIV+1
1)
Resulting f
N
Frequency (in MHz) for
f
VCO
=
400 MHz
f
VCO
=
500 MHz
f
VCO
=
600 MHz
f
VCO
=
700 MHz
≤ 18 ≤ 19 not allowed
19 20 20 25 30 35
20 21 19.05 23.81 28.57 33,33
21 22 18.18 22.73 27.27 31.82
…… ………...
97 98 4.08 5.10 6.12 7.14
98 99 4.04 5.05 6.06 7.07
99
2)
2) This is the default value after a power-on reset.
100 4 5 6 7
≥ 100 ≥ 101 not allowed
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