Infineon Technologies TC1796 - Page 163

TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual 3-14 V2.0, 2007-07
Clock, V2.0
K-Divider
The K-Divider divides the VCO clock f
VCO
by factor K for the CGU output clocks f
CPU
(and
f
SYS
). Table 3-4 shows the K factor values of the K-Divider that are selected by
programming the PLL_CLC.KDIV bit field. It also lists the resulting output clock f
CPU
depending on K and dedicated VCO frequencies. Note that the K-Divider factor is always
PLL_CLC.KDIV+1. For odd K-Divider factors some restrictions for f
CPUmax
must be
regarded.
Note: The shaded selections cannot be used because the maximum TC1796 f
CPU
frequency of 150 MHz is exceeded.
Table 3-4 K-Divider Selections
PLL_CLC.
KDIV
K-Divider:
K=KDIV+1
Resulting f
CPU
Frequency (in MHz) for f
CPU
f
VCO
= 400
MHz
f
VCO
=
500 MHz
f
VCO
=
600 MHz
f
VCO
=
700 MHz
Duty
Cycle
[%]
Max.
Value
[MHz]
01 400 500 600 700
1)
1) These KDIV selections are not allowed in PLL Mode of the TC1796.
1)
12 200 250 300 350
2 3 133.33 166.67 200 233.33 33.33
100
2)
2) This is a restriction in f
CPUmax
for odd K-divider factors.
3 4 100 125 150 175 50 150
4 5 80 100 120 140 40 120
2)
5 6 66.67 83.33 100 116.67 50 150
6 7 57.14 71.43 85.71 100 42.86 130
2)
7 8 50 62.5 75 87.5 50 150
8 9 44 55.56 66.67 77.78 44.44 130
2)
9 10 40 50 60 70 50 150
10 11 36.36 45.45 54.55 63.64 45.45 140
2)
11 12 33.33 41.67 50 58.33 50 150
12 13 30.77 38.46 46.15 53.85 46.15 140
2)
13 14 28.57 35.71 42.86 50 50 150
14 15 26.67 33.33 40 46.67 46.67 145
2)
15
3)
3) This is the default value after a power-on reset.
16 25 31.25 37.5 43.75 50 150