TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-228 V2.0, 2007-07
GPTA, V2.0
The 1. level multiplexer is built up by four 8:1 multiplexers that are controlled in parallel
by bit field LIMLn. Bit field LIMGn controls the 2. level multiplexer and connects one of
the 1. level multiplexer outputs to one of the LIMGng outputs. The output of the 2. level
multiplexer is connected only to the input of an LTC if bit LIMENn is set (enable
multiplexer connection), and bit MRACTL.AEN is set (multiplexer array enabled), and no
reserved bit combination of LIMGn is selected. If one of these conditions is not true, the
corresponding LTC input will be held at a low level.
Two LTC Input Multiplexer Control Registers, LIMCRL and LIMCRH (see also
Page 24-243), are assigned to each of the LTC groups. Therefore, in total sixteen
registers control the connections within the LTC input multiplexer of the LTCA2 module.
The LIMCRL registers control the LIMG output lines 0 to 3 and the GIMCRH registers
control the LIMG output lines 4 to 7. Table 24-20 lists all LTC Input Multiplexer Control
Registers with its control functions. Please note that all LTC Input Multiplexer Control
Registers are not directly accessible but must be written or read using a FIFO array
structure as described on Page 24-229.
Table 24-20 LTC Input Multiplexer Control Register Assignments
LTC Group and LTCs Controlled by
Register
Selectable Groups via
LIMGng
LTCG0 LTC[03:00] LIMCRL0 IOG0, IOG4,
CLOCK, PDL/INT
LTC[07:04] LIMCRH0
LTCG1 LTC[11:08] LIMCRL1 IOG1, CLOCK, PDL/INT
LTC[15:12] LIMCRH1
LTCG2 LTC[19:16] LIMCRL2 IOG2, CLOCK, PDL/INT
LTC[23:20] LIMCRH2
LTCG3 LTC[27:24] LIMCRL3 IOG3, CLOCK, PDL/INT
LTC[31:28] LIMCRH3
LTCG4 LTC[35:32] LIMCRL4 IOG0, IOG4,
CLOCK, PDL/INT
LTC[39:36] LIMCRH4
LTCG5 LTC[43:40] LIMCRL5 IOG1, CLOCK, PDL/INT
LTC[47:44] LIMCRH5
LTCG6 LTC[51:48] LIMCRL6 IOG2, CLOCK, PDL/INT
LTC[55:52] LIMCRH6
LTCG7 LTC[59:56] LIMCRL7 IOG3, CLOCK, PDL/INT
LTC[63:60] LIMCRH7
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