TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-83 V2.0, 2007-07
ADC, V2.0
PCDIS 27 rw Post Calibration Disable
This bit disables the automatic post calibration. Post
calibration takes place after each conversion. The
next conversion is started after the end of the post
calibration. If post calibration, the actual conversion
length increases by two f
ANA
analog clock cycles due
to the post calibration).
0
B
The post calibration is enabled.
1
B
The post calibration is disabled.
CPR 28 rw Clear of Pending Conversion Requests in Parallel
Sources by Arbiter
Bit CPR determines whether or not all pending
conversion requests for an A/D channel, indicated by
STAT.CHNRCC, are cancelled by the arbiter, when
the conversion for this channel has been started.
0
B
The individual clear by arbiter is enabled. Only
the conversion request of channel n of the
winning source is cleared when a conversion of
channel n is started.
1
B
The global clear by arbiter is enabled. All
conversion requests for channel n are cleared
in parallel sources if a conversion of channel n
is started.
SRTEST 31 rw Service Request Test Mode
This bit is used to set a source service request flag
under software control.
0 [14:10],
[26:20],
[30:29]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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