TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-53 V2.0, 2007-07
FADC, V2.0
AC [26:24] rh Addition Count
This bit field indicates the number of additions of filter
input values with remain to be executed before the
next intermediate result register transfer occurs. AC
is loaded with the value of FCRn.ADDL for a new
addition sequence.
CR is cleared when writing GCR.RSTFn = 1.
MAVS [29:28] rh Moving Average State
This bit field indicates how many intermediate
register transfers remain to be executed for the
generation of the next final result.
MAVS = 0 indicates the end of a filter calculation
operation. Since the filter calculation is executed
very fast in comparison to a conversion, MAVS > 0
can be interpreted only as a kind of calculation busy
flag. Therefore, it is recommended to read a valid
filter result from register FRRn only when the
corresponding interrupt request flag CRSR.IRQFn is
set.
MAVS is cleared when writing GCR.RSTFn = 1.
0 [23:18],
27,
[31:30]
r Reserved
Read as 0.
Field Bits Type Description
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