Infineon Technologies TC1796 User Manual

TC1796
System Units (Vol. 1 of 2)
System Control Unit
User’s Manual 5-18 V2.0, 2007-07
SCU, V2.0
LDEN0 10 rw Level Detection Enable 0
This bit determines if bit INTF0 is cleared
automatically if an edge of the input signal IN0 is
detected, which has not been selected (rising edge
with REN0 = 0 or falling edge with FEN0 = 0).
0
B
Bit INTF0 will not be cleared.
1
B
Bit INTF0 will be cleared.
EIEN0 11 rw External Interrupt Enable 0
This bit enables the generation of a trigger event for
request channel 0 (e.g. for interrupt generation) when
a selected edge is detected.
0
B
The trigger event is disabled.
1
B
The trigger event is enabled.
INP0 [14:12] rw Interrupt Node Pointer
This bit field determines the destination (output
channel) for trigger event 0 (if enabled by EIEN0).
X00
B
The event of input channel 0 triggers output
channel 0 (signal INT00).
X01
B
The event of input channel 0 triggers output
channel 1 (signal INT01).
X10
B
The event of input channel 0 triggers output
channel 2 (signal INT02).
X11
B
The event of input channel 0 triggers output
channel 3 (signal INT03).
EXIS1 [21:20] rw External Input Selection 1
This bit field determines which input line is selected
for signal IN1.
00
B
Input IN10 is selected.
01
B
Input IN11 is selected.
10
B
Input IN12 is selected.
11
B
Input IN13 is selected.
FEN1 24 rw Falling Edge Enable 1
This bit determines if the falling edge of signal IN1 is
used to set bit INTF1.
0
B
The falling edge is not used.
1
B
The detection of a falling edge of IN1 generates
a trigger event (INTF1 becomes set).
Field Bits Type Description

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English