TC1796
System Units (Vol. 1 of 2)
Data Memory Unit
User’s Manual 8-5 V2.0, 2007-07
DMU, V2.0
There are four overlay RAM control registers (DMU_IOCRn, n = 0-3) assigned to control
the internal overlay functionality. Each register specifies the start address of an
overlayed 2 Kbyte block within the lower 128 Mbytes of segment 10 and 11. This start
address can be placed on any 2 Kbyte boundary within the external code memory, using
bit field OVPTR.
The principal operation of the address translation process is shown in Figure 8-3.
Figure 8-3 Address Translation Process
In each enabled overlay block control logic, three registers hold the information to control
the overlay functionality:
• The overlay target address in the Overlay Target Address Register OTARx, which
determines the base address of the code memory data block x to be redirected
• The base address of the overlay memory block in the DMU SRAM in the Redirected
Address Base Register RABRx
• A mask in the Overlay Mask Register OMASKx, defining the size of the block, the
address bits to check for an address match, and which bits are used from the target
address and which from the redirected address base
MCA05650
Seg
4 Bits 28 Bits
0000
Compare
matchno match
OTARx
0
0
Destination Address
0
RABRx
OBASE
16 Bits (fix value)
Offset
Programmable
16 Bits (64 KB SRAM)
Redirected Address
Target Address
C000H
Overlay Memory Block x
Offset Address Bits
Overlay Memory Block x
Base Address Bits
OMASKx
111111111 000011111…..
OBASE
TBASE
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