TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-64 V2.0, 2007-07
DMA, V2.0
The Interrupt Status Register indicates if CHSRmx.TCOUNT matches with
CHCRmx.IRDV, or if CHSRmx.TCOUNT has been decremented (depending on
CHICRmx.INTCT[0]),or if a pattern has been detected. These conditions can also
generate an interrupt if enabled (see Figure 12-19 on Page 12-28).
DMA_INTSR
DMA Interrupt Status Register (054
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPM
17
IPM
16
IPM
15
IPM
14
IPM
13
IPM
12
IPM
11
IPM
10
IPM
07
IPM
06
IPM
05
IPM
04
IPM
03
IPM
02
IPM
01
IPM
00
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh
1514131211109876543210
ICH
17
ICH
16
ICH
15
ICH
14
ICH
13
ICH
12
ICH
11
ICH
10
ICH
07
ICH
06
ICH
05
ICH
04
ICH
03
ICH
02
ICH
01
ICH
00
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh
Field Bits Type Description
ICH0x
(x = 0-7)
xrhInterrupt from Channel 0x
This bit indicates that channel 0x has raised an
interrupt for TCOUNT = IRDV or if TCOUNT has
been decremented (depending on CHICR.INTCT[0].
This bit (and IP0x) is cleared by software when
writing a 1 to INTCR.CICH0x or by a channel reset
(writing CHRSTR.CH0x = 1).
0
B
A channel interrupt has not been detected.
1
B
A channel interrupt has been detected.
ICH1x
(x = 0-7)
8+x rh Interrupt from Channel 1x
This bit indicates that channel 1x has raised an
interrupt for TCOUNT = IRDV or if TCOUNT has
been decremented (depending on CHICR.INTCT[0].
This bit (and IP1x) is cleared by software when
writing a 1 to INTCR.CICH1x or by a channel reset
(writing CHRSTR.CH1x = 1).
0
B
A channel interrupt has not been detected.
1
B
A channel interrupt has been detected.
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