Infineon Technologies TC1796 - Page 738

TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-74 V2.0, 2007-07
DMA, V2.0
The DMA Move Engine m (m = 0,1) Access Range Register determines number and size
of the sub-ranges for address range extension n (n = 0-3). See also Figure 12-28 for bit
field definitions.
DMA_ME0ARR
DMA Move Engine 0 Access Range Register
(048
H
) Reset Value: 0000 0000
H
DMA_ME1ARR
DMA Move Engine 1 Access Range Register
(050
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIZE3 SLICE3 SIZE2 SLICE2
rw rw rw rw
1514131211109876543210
SIZE1 SLICE1 SIZE0 SLICE0
rw rw rw rw
Field Bits Type Description
SLICE0 [4:0] rw Address Slice 0
SLICE0 selects a specific sub-range within address
range extension 0.
SIZE0 [7:5] rw Address Size 0
SIZE0 determines the sub-range size within address
range extension 0.
SLICE1 [12:8] rw Address Slice 1
SLICE1 selects a specific sub-range within address
range extension 1.
SIZE1 [15:13] rw Address Size 1
SIZE1 determines the sub-range size within address
range extension 1.
SLICE2 [20:16] rw Address Slice 2
SLICE2 selects a specific sub-range within address
range extension 2.