TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-82 V2.0, 2007-07
DMA, V2.0
Note: The interrupt node of the wrap-around interrupts is shared with the pattern match
interrupt. In order to support interrupt generation in case of a pattern match, the
wrap-around interrupt should be disabled. If the wrap-around interrupts are used,
the pattern match interrupt should not be used. The settings are independent for
each DMA channel.
WRPP [7:4] rw Wrap Pointer
WRPP determines the number n (n = 0-15) of the
service request output SRn that becomes active on a
wrap buffer interrupt.
0000
B
SR0 selected for channel mx wrap buffer
interrupt
0001
B
SR1 selected for channel mx wrap buffer
interrupt
…
B
…
1111
B
SR15 selected for channel mx wrap buffer
interrupt
Note: In the TC1796, only SR[7:0] are connected to
interrupt nodes.
INTP [11:8] rw Interrupt Pointer
INTP determines the number n (n = 0-15) of the service
request output SRn that becomes active on a channel
interrupt.
0000
B
SR0 selected for channel mx interrupt
0001
B
SR1 selected for channel mx interrupt
…
B
…
1111
B
SR15 selected for channel mx interrupt
Note: In the TC1796, only SR[7:0] are connected to
interrupt nodes.
IRDV [15:12] rw Interrupt Raise Detect Value
These bits specify the value of CHSRmx.TCOUNT for
which the Interrupt Threshold Limit should be raised
(m = 0-1).
0 [31:16]
[7:4]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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