Infineon Technologies TC1796 - Page 747

TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-83 V2.0, 2007-07
DMA, V2.0
The Address Control Register controls how source and destination addresses are
updated after a DMA move. Furthermore, it determines whether or not a source or
destination address register update is shadowed.
DMA_ADRCR0x (x = 0-7)
DMA Channel 0x Address Control Register
(x*20
H
+8C
H
) Reset Value: 0000 0000
H
DMA_ADRCR1x (x = 0-7)
DMA Channel 1x Address Control Register
(x*20
H
+18C
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0SHCT
rrw
1514131211109876543210
CBLD CBLS INCD DMF INCS SMF
rw rw rw rw rw rw
Field Bits Type Description
SMF [2:0] rw Source Address Modification Factor
This bit field and the data width as defined in
CHCRmx.CHDW determine an address offset value by
which the source address is modified after each DMA
move. See also Table 12-8.
000
B
Address offset is 1 × CHDW.
001
B
Address offset is 2 × CHDW.
010
B
Address offset is 4 × CHDW.
011
B
Address offset is 8 × CHDW.
100
B
Address offset is 16 × CHDW.
101
B
Address offset is 32 × CHDW.
110
B
Address offset is 64 × CHDW.
111
B
Address offset is 128 × CHDW.