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N2HET Control Registers
1019
SPNU563A–March 2018
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High-End Timer (N2HET) Module
Table 23-16. Global Configuration Register (HETGCR) Field Descriptions (continued)
Bit Field Value Description
16 CMS Clk_master/slave
This bit is used to synchronize multi-N2HETs. If set (N2HET is master), the N2HET outputs a signal
to synchronize the prescalers of the slave N2HET. By default, this bit is reset, which means a slave
configuration.
Note: This bit must be set to one (1) for single-N2HET configuration.
0 N2HET is configured as a slave.
1 N2HET is configured as a master.
15-1 Reserved 0 Reads return 0. Writes have no effect.
0 TO Turn On/Off
TO does not affect the state of the pins. You must set/reset the timer pins when they are turned off,
or re-initialize the timer RAM and control registers before a reset. After a device reset, the timer is
turned off by default.
0 N2HET is OFF. The timer program stops executing. Turn-off is automatically delayed until the
current timer program loop is completed. Turn-off does not affect the content of the timer RAM, ALU
registers, or control registers. Turn-off resets all flags.
1 N2HET is ON. The timer program execution starts synchronously to the Loop clock. In case of
multiple N2HETs configuration, the slave N2HETs are waiting for the loop clock to come from the
master before starting execution. Then, the timer address points automatically address 00h
(corresponding to program start).
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