Instruction Set
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1098
SPNU563A–March 2018
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High-End Timer (N2HET) Module
event The event that triggers the counter.
Table 23-85. Event Encoding Format for ECNT
Event C6 C5 C4 Count Conditions Mode Int. Available
NAF 0 0 0 NAF flag is Set Angle counter Y
FALL 0 0 1 Falling edge on selected pin Event counter Y
RISE 0 1 0 Rising edge on selected pin Event counter Y
BOTH 0 1 1
Rising and Falling edge on
selected pin
Event counter Y
ACCUHIGH 1 0 - while pin is high level Pulse accumulation N
ACCULOW 1 1 - while pin is low level Pulse accumulation N
irq ON generates an interrupt when event in counter mode occurs. No
interrupt is generated with OFF.
Default: OFF.
data 25-bit integer value serving as a counter.
Default: 0.
Execution
If (event occurs)
{
If (Register A or B Selected) {
Selected register = Immediate Data Field + 1;
}
If (Register R, S or T Selected)
{
Selected register[31:7] = Immediate Data Field + 1;
Selected register[6:0] = 0;
}
Immediate Data Field = Immediate Data Field + 1;
If (Interrupt Enable == 1) HETFLG[n] = 1; /* n depends on address */
If ([C28:C27] == 01) Generate request on line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on line [P25:P23];
Jump to Conditional Address;
}
else
{
Jump to Next Program Address;
}
Prv bit = Current Logic (Lx) value of selected pin; (Always executed)
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 23.2.7.
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