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Instruction Set
1113
SPNU563A–March 2018
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High-End Timer (N2HET) Module
Cycles One
Register modified Selected register (A, B or T)
Description This instruction defines a virtual timer used to generate variable length pulses.
The counter value stored in the data field is decremented unconditionally on
each timer resolution until it reaches zero, and it then stays at zero until it is
reloaded with a non-zero value.
The specified pin action is performed as long as the count after count value is
decremented is greater than 0. The opposite pin action is performed when the
count after decrement just reaches 0.
If the hr_lr bit is reset, the opposite pin action will be taken after a HR delay
from the next loop resolution clock. If the hr_lr bit is set, the delay is ignored.
This delay is programmed in bits [D6:D0].
irq ON generates an interrupt when the data field value reaches 0. No
interrupt is generated for OFF.
Default: OFF.
data 25-bit integer value serving as a counter.
hr_data HR delay.
Default: 0.
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