GIO Control Registers
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SPNU563A–March 2018
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General-Purpose Input/Output (GIO) Module
25.5.4.2 GIOENACLR Register
This register disables the interrupt. Figure 25-9 and Table 25-6 describe this register.
Figure 25-9. GIO Interrupt Enable Clear Register (GIOENACLR) [offset = 14h]
31 24 23 16
GIOENACLR 3 GIOENACLR 2
R/W-0 R/W-0
15 8 7 0
GIOENACLR 1 GIOENACLR 0
R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 25-6. GIO Interrupt Enable Clear Register (GIOENACLR) Field Descriptions
Bit Field Value Description
31-24 GIOENACLR 3 Interrupt disable for pins GIOD[7:0]
0 Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1 Read: The interrupt is enabled.
Write: Disables the interrupt.
23-16 GIOENACLR 2 Interrupt disable for pins GIOC[7:0]
0 Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1 Read: The interrupt is enabled.
Write: Disables the interrupt.
15-8 GIOENACLR 1 Interrupt disable for pins GIOB[7:0]
0 Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1 Read: The interrupt is enabled.
Write: Disables the interrupt.
7-0 GIOENACLR 0 Interrupt disable for pins GIOA[7:0]
0 Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1 Read: The interrupt is enabled.
Write: Disables the interrupt.
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