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Module Operation
1271
SPNU563A–March 2018
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FlexRay Module
26.2.14.1.2 Enable Interrupts
TSMIES/R and TCCIES/R control the buffer transfer interrupts for each buffer in both directions. The
TEIRES/R registers controls the maskable error interrupt sources which are:
• VBUS transaction errors
If an error occurs during VBUS read or write transfer a error interrupt will be generated.
• Forbidden access to IBF or OBF
Since host accesses to communication controller through the IBF and the OBF (0x400-0x7FF) are
forbidden, as long as the Transfer Unit State Machine is enabled, accesses will be ignored and an
error interrupt will be generated.
• Transfer not ready when TBA should be loaded
When a transfer is ongoing/pending during base address reload on FlexRay communication cycle start
(only occurs if NTBA != TBA) the TBA will not be loaded and an error interrupt will be generated.
The transfer interrupts use a separate interrupt line (TU_int0) than the error interrupts (TU_int1).
26.2.14.1.3 Interrupt Flags
The TSMO and TCCO flags indicate buffer transfer status interrupts whereas the TEIF flags indicate
interrupt sources for maskable and non-maskable error interrupts.
The error interrupt flags are set by the Transfer Unit State Machine and can be cleared by the CPU by
writing a 1. If the CPU clears the flag, while the Transfer Unit State Machine sets it at the same time, the
flag remains set.
26.2.14.1.4 Nonmaskable Error Indication
Memory protection violation and uncorrectable TCR error have their own nonmaskable error lines, which
can be connected to the Vectored Interrupt Module (VIM) and/or the Error Signaling Module (ESM). Refer
to the device-specific data manual on the hookup.
• If a memory protection violation occurs, the Memory Protection Violation Error (TU_MPV_err) line will
be activated.
• If an uncorrectable TCR error occurs while accessing the TCR, the ECC Error (TU_UCT_err) line will
be activated. An uncorrectable TCR error can be caused by an ECC error in TCR.
26.2.14.2 Communication Controller Interrupts
In general, interrupts provide a close link to the protocol timing as they are triggered almost immediately
when an error or status change is detected by the controller, a frame is received or transmitted, a
configured timer interrupt is activated, or a stop watch event occurred. This enables the host CPU to react
very quickly on specific error conditions, status changes, or timer events. To remain flexible though, the
communication controller supports disable / enable controls for each individual interrupt source separately.
An interrupt may be triggered, for example, when:
• a frame is received or transmitted
• an error was detected
• a status flag is set
• a timer reaches a preconfigured value
• a message transfer from input buffer to message RAM or from message RAM to output buffer has
completed
• a stop watch event occurred
NOTE: For specific information about error interrupt generation on uncorrectable RAM errors, see
Figure 26-30.
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