Texas Instruments TMS570LC4357 - Page 13

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13
SPNU563A–March 2018
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Contents
19.5 Interrupt Vector Table (VIM RAM)...................................................................................... 672
19.5.1 Interrupt Vector Table Operation ............................................................................. 672
19.5.2 VIM ECC Syndrome............................................................................................ 673
19.5.3 Interrupt Vector Table Initialization ........................................................................... 674
19.5.4 Interrupt Vector Table ECC Testing.......................................................................... 674
19.6 VIM Wakeup Interrupt.................................................................................................... 676
19.7 Capture Event Sources .................................................................................................. 677
19.8 Examples .................................................................................................................. 677
19.8.1 Examples - Configure CPU To Receive Interrupts......................................................... 677
19.8.2 Examples - Register Vector Interrupt and Index Interrupt Handling ..................................... 678
19.9 VIM Control Registers.................................................................................................... 680
19.9.1 Interrupt Vector Table ECC Status Register (ECCSTAT) ................................................ 681
19.9.2 Interrupt Vector Table ECC Control Register (ECCCTL).................................................. 682
19.9.3 Uncorrectable Error Address Register (UERRADDR) ..................................................... 683
19.9.4 Fallback Vector Address Register (FBVECADDR)......................................................... 683
19.9.5 Single-Bit Error Address Register (SBERRADDR)......................................................... 684
19.9.6 VIM Offset Vector Registers................................................................................... 684
19.9.7 IRQ Index Offset Vector Register (IRQINDEX)............................................................. 685
19.9.8 FIQ Index Offset Vector Registers (FIQINDEX) ............................................................ 685
19.9.9 FIQ/IRQ Program Control Registers (FIRQPR[0:3]) ....................................................... 686
19.9.10 Pending Interrupt Read Location Registers (INTREQ[0:3]) ............................................. 687
19.9.11 Interrupt Enable Set Registers (REQENASET[0:3])...................................................... 688
19.9.12 Interrupt Enable Clear Registers (REQENACLR[0:3]) ................................................... 689
19.9.13 Wake-Up Enable Set Registers (WAKEENASET[0:3])................................................... 690
19.9.14 Wake-Up Enable Clear Registers (WAKEENACLR[0:3]) ................................................ 691
19.9.15 IRQ Interrupt Vector Register (IRQVECREG)............................................................. 692
19.9.16 FIQ Interrupt Vector Register (FIQVECREG) ............................................................. 692
19.9.17 Capture Event Register (CAPEVT) ......................................................................... 693
19.9.18 VIM Interrupt Control Registers (CHANCTRL[0:31]) ..................................................... 694
20 Direct Memory Access Controller (DMA) Module .................................................................. 696
20.1 Overview ................................................................................................................... 697
20.1.1 Main Features................................................................................................... 697
20.1.2 System Resources Mapping .................................................................................. 699
20.2 Module Operation......................................................................................................... 699
20.2.1 Memory Space .................................................................................................. 700
20.2.2 DMA Data Access .............................................................................................. 700
20.2.3 Addressing Modes.............................................................................................. 701
20.2.4 DMA Channel Control Packets ............................................................................... 701
20.2.5 Priority Queue................................................................................................... 705
20.2.6 Data Packing and Unpacking ................................................................................. 707
20.2.7 DMA Request ................................................................................................... 710
20.2.8 Auto-Initiation.................................................................................................... 712
20.2.9 Interrupts......................................................................................................... 712
20.2.10 Debugging...................................................................................................... 714
20.2.11 Power Management .......................................................................................... 714
20.2.12 FIFO Buffer..................................................................................................... 715
20.2.13 Channel Chaining ............................................................................................. 716
20.2.14 Request Polarity............................................................................................... 716
20.2.15 Memory Protection ............................................................................................ 717
20.2.16 ECC Checking................................................................................................. 718
20.2.17 ECC Testing ................................................................................................... 719
20.2.18 Initializing RAM with ECC.................................................................................... 719
20.2.19 Transaction Errors ............................................................................................ 720