Texas Instruments TMS570LC4357 - Page 14

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14
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
20.3 Control Registers and Control Packets ................................................................................ 721
20.3.1 Global Configuration Registers ............................................................................... 724
20.3.2 Channel Configuration ......................................................................................... 788
21 External Memory Interface (EMIF) ....................................................................................... 793
21.1 Introduction ................................................................................................................ 794
21.1.1 Purpose of the Peripheral ..................................................................................... 794
21.1.2 Features.......................................................................................................... 794
21.1.3 Functional Block Diagram ..................................................................................... 795
21.2 EMIF Module Architecture............................................................................................... 796
21.2.1 EMIF Clock Control............................................................................................. 796
21.2.2 EMIF Requests.................................................................................................. 796
21.2.3 EMIF Signal Descriptions...................................................................................... 796
21.2.4 EMIF Signal Multiplexing Control............................................................................. 797
21.2.5 SDRAM Controller and Interface ............................................................................. 798
21.2.6 Asynchronous Controller and Interface ...................................................................... 810
21.2.7 Data Bus Parking ............................................................................................... 822
21.2.8 Reset and Initialization Considerations ...................................................................... 823
21.2.9 Interrupt Support................................................................................................ 823
21.2.10 DMA Event Support........................................................................................... 824
21.2.11 EMIF Signal Multiplexing..................................................................................... 824
21.2.12 Memory Map................................................................................................... 824
21.2.13 Priority and Arbitration........................................................................................ 825
21.2.14 System Considerations....................................................................................... 826
21.2.15 Power Management .......................................................................................... 827
21.2.16 Emulation Considerations.................................................................................... 827
21.3 EMIF Registers............................................................................................................ 828
21.3.1 Module ID Register (MIDR) ................................................................................... 828
21.3.2 Asynchronous Wait Cycle Configuration Register (AWCC)............................................... 829
21.3.3 SDRAM Configuration Register (SDCR) .................................................................... 830
21.3.4 SDRAM Refresh Control Register (SDRCR)................................................................ 831
21.3.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) .......................................... 832
21.3.6 SDRAM Timing Register (SDTIMR).......................................................................... 833
21.3.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) .................................................. 834
21.3.8 EMIF Interrupt Raw Register (INTRAW)..................................................................... 835
21.3.9 EMIF Interrupt Masked Register (INTMSK) ................................................................. 836
21.3.10 EMIF Interrupt Mask Set Register (INTMSKSET) ........................................................ 837
21.3.11 EMIF Interrupt Mask Clear Register (INTMSKCLR)...................................................... 838
21.3.12 Page Mode Control Register (PMCR)...................................................................... 839
21.4 Example Configuration................................................................................................... 840
21.4.1 Hardware Interface ............................................................................................. 840
21.4.2 Software Configuration......................................................................................... 840
22 Analog To Digital Converter (ADC) Module .......................................................................... 848
22.1 Overview .................................................................................................................. 849
22.1.1 Introduction ..................................................................................................... 851
22.2 Basic Operation ........................................................................................................... 853
22.2.1 Basic Features and Usage of the ADC ..................................................................... 853
22.2.2 Advanced Conversion Group Configuration Options ...................................................... 860
22.2.3 ADC Module Basic Interrupts ................................................................................ 868
22.2.4 ADC Module DMA Requests ................................................................................. 869
22.2.5 ADC Magnitude Threshold Interrupts ....................................................................... 870
22.2.6 ADC Special Modes............................................................................................ 871
22.2.7 ADC Results’ RAM Special Features ........................................................................ 878
22.2.8 ADEVT Pin General Purpose I/O Functionality............................................................. 879