Texas Instruments TMS570LC4357 - Page 15

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15
SPNU563A–March 2018
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Contents
22.3 ADC Registers ............................................................................................................ 881
22.3.1 ADC Reset Control Register (ADRSTCR) .................................................................. 883
22.3.2 ADC Operating Mode Control Register (ADOPMODECR) ............................................... 883
22.3.3 ADC Clock Control Register (ADCLOCKCR) .............................................................. 885
22.3.4 ADC Calibration Mode Control Register (ADCALCR) ..................................................... 885
22.3.5 ADC Event Group Operating Mode Control Register (ADEVMODECR) ................................ 887
22.3.6 ADC Group1 Operating Mode Control Register (ADG1MODECR) ...................................... 890
22.3.7 ADC Group2 Operating Mode Control Register (ADG2MODECR) ...................................... 893
22.3.8 ADC Event Group Trigger Source Select Register (ADEVSRC) ......................................... 896
22.3.9 ADC Group1 Trigger Source Select Register (ADG1SRC) ............................................... 897
22.3.10 ADC Group2 Trigger Source Select Register (ADG2SRC).............................................. 898
22.3.11 ADC Event Interrupt Enable Control Register (ADEVINTENA) ......................................... 899
22.3.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA)....................................... 900
22.3.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA)....................................... 901
22.3.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG).............................................. 902
22.3.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG).................................................... 903
22.3.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG).................................................... 904
22.3.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) ......................... 905
22.3.18 ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) ............................... 905
22.3.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) ............................... 906
22.3.20 ADC Event Group DMA Control Register (ADEVDMACR) .............................................. 907
22.3.21 ADC Group1 DMA Control Register (ADG1DMACR) .................................................... 909
22.3.22 ADC Group2 DMA Control Register (ADG2DMACR) .................................................... 911
22.3.23 ADC Results Memory Configuration Register (ADBNDCR) ............................................. 913
22.3.24 ADC Results Memory Size Configuration Register (ADBNDEND) ..................................... 914
22.3.25 ADC Event Group Sampling Time Configuration Register (ADEVSAMP)............................. 915
22.3.26 ADC Group1 Sampling Time Configuration Register (ADG1SAMP) ................................... 915
22.3.27 ADC Group2 Sampling Time Configuration Register (ADG2SAMP) ................................... 916
22.3.28 ADC Event Group Status Register (ADEVSR) ............................................................ 917
22.3.29 ADC Group1 Status Register (ADG1SR) .................................................................. 918
22.3.30 ADC Group2 Status Register (ADG2SR) .................................................................. 919
22.3.31 ADC Event Group Channel Select Register (ADEVSEL)................................................ 920
22.3.32 ADC Group1 Channel Select Register (ADG1SEL) ...................................................... 921
22.3.33 ADC Group2 Channel Select Register (ADG2SEL) ...................................................... 922
22.3.34 ADC Calibration and Error Offset Correction Register (ADCALR)...................................... 923
22.3.35 ADC State Machine Status Register (ADSMSTATE) .................................................... 923
22.3.36 ADC Channel Last Conversion Value Register (ADLASTCONV) ...................................... 924
22.3.37 ADC Event Group Results' FIFO Register (ADEVBUFFER) ............................................ 925
22.3.38 ADC Group1 Results FIFO Register (ADG1BUFFER)................................................... 926
22.3.39 ADC Group2 Results FIFO Register (ADG2BUFFER)................................................... 927
22.3.40 ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER).......................... 928
22.3.41 ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) ................................ 929
22.3.42 ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) ................................ 930
22.3.43 ADC ADEVT Pin Direction Control Register (ADEVTDIR) .............................................. 931
22.3.44 ADC ADEVT Pin Output Value Control Register (ADEVTOUT) ........................................ 932
22.3.45 ADC ADEVT Pin Input Value Register (ADEVTIN)....................................................... 932
22.3.46 ADC ADEVT Pin Set Register (ADEVTSET).............................................................. 933
22.3.47 ADC ADEVT Pin Clear Register (ADEVTCLR) ........................................................... 933
22.3.48 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) .......................................... 934
22.3.49 ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) ......................................... 934
22.3.50 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) .......................................... 935
22.3.51 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) .................. 935
22.3.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) ........................ 936