ADC Registers
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SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR)
The ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) is shown in Figure 22-41 and
described in Table 22-25.
Figure 22-41. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) [offset = 48h]
31 16 15 9 8 0
Reserved Sign Extension G2_THR
R-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-25. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR)
Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-9 Sign Extension These bits always read the same as G2_THR bit 8 of this register.
8-0 G2_THR Group2 Threshold Counter.
Before ADC conversions begin on the Group2, this field is initialized to the number of conversion
results that the Group2 memory should contain before interrupting the CPU. This counter
decrements when the ADC module writes a new conversion result to the Group2 results’ memory.
The counter increments for each read of a conversion result from the Group2 results’ memory in the
“read from FIFO” mode. The threshold counter is not affected for a direct read from the group2
results’ memory. Also, a simultaneous ADC write and a CPU/DMA read from the Group2 FIFO will
leave the threshold counter unchanged. In case of an Group2 Results’ memory overrun condition, if
new conversion results are not allowed to overwrite the existing memory contents, then the Grou21
threshold counter is not decremented.
Refer to Section 22.2.3.2 for more details on the threshold interrupts.
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