ADC Registers
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SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA)
ADC Group1 Interrupt Enable Control Register (ADG1INTENA) is shown in Figure 22-34 and described in
Table 22-18.
Figure 22-34. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) [offset = 2Ch]
31 8
Reserved
R-0
7 4 3 2 1 0
Reserved G1_END_
INT_EN
Reserved G1_OVR_
INT_EN
G1_THR_
INT_EN
R-0 R/W-0 R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-18. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reads return 0. Writes have no effect.
3 G1_END_INT_EN Group1 Conversion End Interrupt Enable. Refer to Section 22.2.3.1 for more details on the
conversion end interrupts.
Any operation mode read/write:
0 No interrupt is generated when conversion of all the channels selected for conversion in the
Group1 is done.
1 A Group1 conversion end interrupt is generated when conversion of all the channels selected
for conversion in the Group1 is done.
2 Reserved 0 Reads return 0. Writes have no effect.
1 G1_OVR_INT_EN Group1 Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries to
write a new conversion result to the Group1 results memory which is already full. For more
details on the overrun interrupts Refer to Section 22.2.3.3.
Any operation mode read/write:
0 No interrupt is generated if a Group1 memory overrun occurs.
1 A Group1 memory overrun interrupt is generated if a Group1 memory overrun condition occurs.
0 G1_THR_INT_EN Group1 Threshold Interrupt Enable. A Group1 threshold interrupt occurs when the programmed
Group1 threshold counter counts down to 0. Refer to Section 22.2.3.2 for more details.
Any operation mode read/write:
0 No interrupt is generated if the Group1 threshold counter reaches 0.
1 A Group1 threshold interrupt is generated if the Group1 threshold counter reaches 0.
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