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ADC Registers
901
SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA)
ADC Group2 Interrupt Enable Control Register (ADG2INTENA) is shown in Figure 22-35 and described in
Table 22-19.
Figure 22-35. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) [offset = 30h]
31 8
Reserved
R-0
7 4 3 2 1 0
Reserved G2_END_
INT_EN
Reserved G2_OVR_
INT_EN
G2_THR_
INT_EN
R-0 R/W-0 R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-19. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reads return 0. Writes have no effect.
3 G2_END_INT_EN Group2 Conversion End Interrupt Enable. Refer to Section 22.2.3.1 for more details on the
conversion end interrupts.
Any operation mode read/write:
0 No interrupt is generated when conversion of all the channels selected for conversion in the
Group2 is done.
1 A Group2 conversion end interrupt is generated when conversion of all the channels selected
for conversion in the Group2 is done.
2 Reserved 0 Reads return 0. Writes have no effect.
1 G2_OVR_INT_EN Group2 Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries to
write a new conversion result to the Group2 results memory which is already full. For more
details on the overrun interrupts, refer to Section 22.2.3.3.
Any operation mode read/write:
0 No interrupt is generated if a Group2 memory overrun occurs.
1 A Group2 memory overrun interrupt is generated if a Group2 memory overrun condition occurs.
0 G2_THR_INT_EN Group2 Threshold Interrupt Enable. A Group2 threshold interrupt occurs when the programmed
Group2 threshold counter counts down to 0. Refer to Section 22.2.3.2 for more details.
Any operation mode read/write:
0 No interrupt is generated if the Group2 threshold counter reaches 0.
1 A Group2 threshold interrupt is generated if the Group2 threshold counter reaches 0.
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