ADC Registers
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SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.48 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR)
ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) is shown in Figure 22-77 and described in
Table 22-54.
Figure 22-77. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) [offset = 110h]
31 1 0
Reserved ADEVT_PDR
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-54. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 ADEVT_PDR ADEVT Pin Open Drain Enable. This bit enables the open-drain capability for the ADEVT pin if it is
configured to be an output and a logic HIGH is being driven on to the pin.
Any operating mode read/write:
0 Output value on the ADEVT pin is logic HIGH.
1 The ADEVT pin is tristated.
22.3.49 ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS)
ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) is shown in Figure 22-78 and described in
Table 22-55.
Figure 22-78. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) [offset = 114h]
31 1 0
Reserved ADEVT_PDIS
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-55. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 ADEVT_PDIS ADEVT Pin Pull Control Disable. This bit enables or disables the pull control on the ADEVT pin if it
is configured to be an input pin.
Any operating mode read/write:
0 Pull on ADEVT pin is enabled.
1 Pull on ADEVT pin is disabled.
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