ADC Registers
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SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.33 ADC Group2 Channel Select Register (ADG2SEL)
ADC Group2 Channel Select Register (ADG2SEL) is shown in Figure 22-55 and described in Table 22-39.
NOTE: Clearing ADG2SEL During a Conversion
Writing 0x0000 to ADG2SEL stops the Group2 conversions. This does not cause the ADC
Group2 Results Memory pointer or the Group2 Threshold Register to be reset.
NOTE: Writing A Non-Zero Value To ADG2SEL During a Conversion
Writing a new value to ADG2SEL while a Channel in Group2 is being converted results in a
new conversion sequence starting immediately with the highest priority channel in the new
ADG2SEL selection. This also causes the ADC Group2 Results Memory pointer to be reset
so that the memory allocated for storing the Group2 conversion results gets overwritten.
Care should be taken to re-program the corresponding Interrupt Threshold Counter or DMA
Threshold Counter again so that correct number of conversions happen before a Threshold
interrupt or Block DMA request is generated.
ADC1 supports up to 32 channels and ADC2 supports up to 25 channels on the microcontroller.
Figure 22-55. ADC Group2 Channel Select Register (ADG2SEL) [offset = 80h]
31 0
G2_SEL
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 22-39. ADC Group2 Channel Select Register (ADG2SEL) Field Descriptions
Bit Field Value Description
31-0 G2_SEL Group2 channels selected.
Any operation mode read/write:
0 No ADC input channel is selected for conversion in the Group2.
Non-zero The channels marked by the bit positions that are set to 1 will be converted in ascending
order when the Group2 is triggered.
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