ADC Registers
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SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.31 ADC Event Group Channel Select Register (ADEVSEL)
ADC Event Group Channel Select Register (ADEVSEL) is shown in Figure 22-53 and described in
Table 22-37.
NOTE: Clearing ADEVSEL During a Conversion
Writing 0x0000 to ADEVSEL stops the Event Group conversions. This does not cause the
ADC Event Group Results Memory pointer or the Event Group Threshold Register to be
reset.
NOTE: Writing A Non-Zero Value To ADEVSEL During a Conversion
Writing a new value to ADEVSEL while a Channel in Event Group is being converted results
in a new conversion sequence starting immediately with the highest priority channel in the
new ADEVSEL selection. This also causes the ADC Event Group Results Memory pointer to
be reset so that the memory allocated for storing the Event Group conversion results gets
overwritten. Care should be taken to re-program the corresponding Interrupt Threshold
Counter or DMA Threshold Counter again so that correct number of conversions happen
before a Threshold interrupt or Block DMA request is generated.
ADC1 supports up to 32 channels and ADC2 supports up to 25 channels on the microcontroller.
Figure 22-53. ADC Event Group Channel Select Register (ADEVSEL) [offset = 78h]
31 0
EV_SEL
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 22-37. ADC Event Group Channel Select Register (ADEVSEL) Field Descriptions
Bit Field Value Description
31-0 EV_SEL Event Group channels selected.
Any operation mode read/write:
0 No ADC input channel is selected for conversion in the Event Group.
Non-zero The channels marked by the bit positions that are set to 1 will be converted in ascending
order when the Event Group is triggered.
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