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ADC Registers
919
SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.30 ADC Group2 Status Register (ADG2SR)
ADC Group2 Status Register (ADG2SR) is shown in Figure 22-52 and described in Table 22-36.
Figure 22-52. ADC Group2 Status Register (ADG2SR) [offset = 74h]
31 8
Reserved
R-0
7 4 3 2 1 0
Reserved G2_MEM_
EMPTY
G2_BUSY G2_STOP G2_END
R-0 R-1 R-0 R-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 22-36. ADC Group2 Status Register (ADG2SR) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reads return 0. Writes have no effect.
3 G2_MEM_EMPTY Group2 Results Memory Empty. This bit can be effectively used only when the conversion
results are read out of the Group2 results memory in the "read from FIFO" mode.
Any operation mode read:
0 The Group2 results memory has valid conversion results.
1 The Group2 results memory is empty, or does not contain any unread conversion results.
2 G2_BUSY Group2 Conversion Busy.
Any operation mode read:
0 Group2 conversions are neither in progress nor frozen.
1 Group2 conversions are either in progress, or are frozen for servicing some other group. This
bit will always be set when the Group2 is configured to be in the continuous conversion mode.
1 G2_STOP Group2 Conversion Stopped.
Any operation mode read:
0 Group2 conversions are not currently frozen.
1 Group2 conversions are currently frozen.
0 G2_END Group2 Conversions Ended.
Any operation mode read:
0 Group2 conversions have either not been started or have not yet completed since the last time
this status bit was cleared.
1 The conversion for all the channels selected in the Group2 has completed. This bit can be
cleared under the following conditions:
• By reading a conversion result from the Group2 results memory in the "read from FIFO"
mode.
• By writing a new value to the Group2 channel select register (ADG2SEL).
• By writing a 1 to this bit.
• By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control
register (ADOPMODECR).
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