www.ti.com
ADC Registers
881
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Analog To Digital Converter (ADC) Module
22.3 ADC Registers
All registers in the ADC module are 32-bit, word-aligned; 8-bit, 16-bit and 32-bit accesses are allowed.
The application must ensure that the reserved bits are always written as 0 to ensure software compatibility
to future revisions of the module. Table 22-6 shows register address offsets from the base address of the
ADC modules. The base address of ADC1 registers is FFF7 C000h and the base address of ADC2
registers is FFF7 C200h.
Table 22-6. ADC Registers
Offset Acronym Register Description Section
00h ADRSTCR ADC Reset Control Register Section 22.3.1
04h ADOPMODECR ADC Operating Mode Control Register Section 22.3.2
08h ADCLOCKCR ADC Clock Control Register Section 22.3.3
0Ch ADCALCR ADC Calibration Mode Control Register Section 22.3.4
10h ADEVMODECR ADC Event Group Operating Mode Control Register Section 22.3.5
14h ADG1MODECR ADC Group1 Operating Mode Control Register Section 22.3.6
18h ADG2MODECR ADC Group2 Operating Mode Control Register Section 22.3.7
1Ch ADEVSRC ADC Trigger Source Select Register Section 22.3.8
20h ADG1SRC ADC Group1 Trigger Source Select Register Section 22.3.9
24h ADG2SRC ADC Group2 Trigger Source Select Register Section 22.3.10
28h ADEVINTENA ADC Event Interrupt Enable Control Register Section 22.3.11
2Ch ADG1INTENA ADC Group1 Interrupt Enable Control Register Section 22.3.12
30h ADG2INTENA ADC Group2 Interrupt Enable Control Register Section 22.3.13
34h ADEVINTFLG ADC Event Group Interrupt Flag Register Section 22.3.14
38h ADG1INTFLG ADC Group1 Interrupt Flag Register Section 22.3.15
3Ch ADG2INTFLG ADC Group2 Interrupt Flag Register Section 22.3.16
40h ADEVTHRINTCR ADC Event Group Threshold Interrupt Control Register Section 22.3.17
44h ADG1THRINTCR ADC Group1 Threshold Interrupt Control Register Section 22.3.18
48h ADG2THRINTCR ADC Group2 Threshold Interrupt Control Register Section 22.3.19
4Ch ADEVDMACR ADC Event Group DMA Control Register Section 22.3.20
50h ADG1DMACR ADC Group1 DMA Control Register Section 22.3.21
54h ADG2DMACR ADC Group2 DMA Control Register Section 22.3.22
58h ADBNDCR ADC Results Memory Configuration Register Section 22.3.23
5Ch ADBNDEND ADC Results Memory Size Configuration Register Section 22.3.24
60h ADEVSAMP ADC Event Group Sampling Time Configuration Register Section 22.3.25
64h ADG1SAMP ADC Group1 Sampling Time Configuration Register() Section 22.3.26
68h ADG2SAMP ADC Group2 Sampling Time Configuration Register Section 22.3.27
6Ch ADEVSR ADC Event Group Status Register Section 22.3.28
70h ADG1SR ADC Group1 Status Register Section 22.3.29
74h ADG2SR ADC Group2 Status Register Section 22.3.30
78h ADEVSEL ADC Event Group Channel Select Register Section 22.3.31
7Ch ADG1SEL ADC Group1 Channel Select Register Section 22.3.32
80h ADG2SEL ADC Group2 Channel Select Register Section 22.3.33
84h ADCALR ADC Calibration and Error Offset Correction Register Section 22.3.34
88h ADSMSTATE ADC State Machine Status Register Section 22.3.35
8Ch ADLASTCONV ADC Channel Last Conversion Value Register Section 22.3.36
90h-AFh ADEVBUFFER ADC Event Group Results FIFO Register Section 22.3.37
B0h-CFh ADG1BUFFER ADC Group1 Results FIFO Register Section 22.3.38
D0h-EFh ADG2BUFFER ADC Group2 Results FIFO Register Section 22.3.39
F0h ADEVEMUBUFFER ADC Event Group Results Emulation FIFO Register Section 22.3.40
F4h ADG1EMUBUFFER ADC Group1 Results Emulation FIFO Register Section 22.3.41
To Next Page
Loading...
Need help?
General
