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ADC Registers
903
SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG)
ADC Group1 Interrupt Flag Register (ADG1INTFLG) is shown in Figure 22-37 and described in Table 22-
21.
Figure 22-37. ADC Group1 Interrupt Flag Register (ADG1INTFLG) [offset = 38h]
31 8
Reserved
R-0
7 4 3 2 1 0
Reserved G1_END G1_MEM_
EMPTY
G1_MEM_
OVERRUN
G1_THR_
INT_FLG
R-0 R/W1C-0 R-1 R-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 22-21. ADC Group1 Interrupt Flag Register (ADG1INTFLG) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reads return 0. Writes have no effect.
3 G1_END Group1 Conversion End. This bit will be set only if the Group1 conversions are configured to be
in the single-conversion mode.
Any operation mode read:
0 All the channels selected for conversion in the Group1 have not yet been converted.
1 All the channels selected for conversion in the Group1 have been converted. A Group1
conversion end interrupt is generated, if enabled, when this bit gets set.
This bit can be cleared by any one of the following ways:
• By writing a 1 to this bit
• By writing a 1 to the Group1 status register (ADG1SR) bit 0 (G1_END)
• By reading one conversion result from the Group1 results’ memory in the “read from FIFO”
mode
• By writing a new set of channels to the Group1 channel select register
2 G1_MEM_EMPTY Group1 Results Memory Empty. This is a read-only bit; writes have no effect. It is not a source
of an interrupt from the ADC module.
Any operation mode read:
0 The Group1 results memory is not empty.
1 The Group1 results memory is empty.
1 G1_MEM_OVERRUN Group1 Memory Overrun. This is a read-only bit; writes have no effect.
Any operation mode read:
0 Group1 results memory has not overrun.
1 Group1 results memory has overrun.
0 G1_THR_INT_FLG Group1 Threshold Interrupt Flag.
Any operation mode read:
0 The number of conversions completed for the Group1 is smaller than the threshold
programmed in the Group1 interrupt threshold register.
1 The number of conversions completed for the Group1 is equal to or greater than the threshold
programmed in the Group1 interrupt threshold register.
This bit can be cleared by writing a 1; writing a 0 has no effect.