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ADC Registers
909
SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.21 ADC Group1 DMA Control Register (ADG1DMACR)
ADC Group1 DMA Control Register (ADG1DMACR) is shown in Figure 22-43 and described in Table 22-
27.
Figure 22-43. ADC Group1 DMA Control Register (ADG1DMACR) [offset = 50h]
31 25 24 16
Reserved G1_BLOCKS
R-0 R/W-0
15 8
Reserved
R-0
7 4 3 2 1 0
Reserved DMA_G1_END G1_BLK_XFER Reserved G1_DMA_EN
R-0 R/W-0 R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-27. ADC Group1 DMA Control Register (ADG1DMACR) Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Reads return 0. Writes have no effect.
24-16 G1_BLOCKS Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured
to generate a DMA request. If the Group1 is configured to use the block transfer mode of the
DMA module, then the ADC module generates a DMA request after the Group1 results’
memory accumulates G1_BLOCKS number of conversion results.
This feature is designed to be used in place of the threshold interrupt for the Group1. As a
result, the G1_THR field of the Group1 Interrupt Threshold Control Register and the
G1_BLOCKS field of the Group1 DMA Control Register are the same.
Any operation mode read/write:
0 No DMA transfer occurs even if G1_BLK_XFER is set to 1.
1h-1FFh One DMA request is generated if the G1_BLK_XFER is set to 1 and the specified number of
Group1 conversion results have been accumulated.
15-4 Reserved 0 Reads return 0. Writes have no effect.
3 DMA_G1_END Group1 Conversion End DMA Transfer Enable.
Any operation mode read:
0 ADC module generates a DMA request for each write to the group1 results RAM if
G1_DMA_EN is set.
1 ADC module generates a DMA request when the ADC has completed the conversions for all
channels selected for conversion in the group1.
If DMA_G1_END bit is set to 1, G1_DMA_EN bit is ignored and DMA requests will be
generated every time the DMA_G1_END flag in the group 1 status register is set. The
DMA_G1_END bit must be set before enabling conversions for the group 1.
2 G1_BLK_XFER Group1 Block DMA Transfer Enable.
Any operation mode read:
0 ADC module generates a DMA request for each write to the Group1 memory if G1_DMA_EN is
set.
1 ADC module generates a DMA request when the ADC has written G1_BLOCKS number of
buffers into the Group1 memory.
If G1_BLK_XFER bit is set to 1, G1_DMA_EN bit is ignored and DMA requests will be
generated every time the Threshold Counter reaches 0 from a count value of 1.
1 Reserved 0 Reads return 0. Writes have no effect.
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