www.ti.com
ADC Registers
917
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Analog To Digital Converter (ADC) Module
22.3.28 ADC Event Group Status Register (ADEVSR)
ADC Event Group Status Register (ADEVSR) is shown in Figure 22-50 and described in Table 22-34.
Figure 22-50. ADC Event Group Status Register (ADEVSR) [offset = 6Ch]
31 8
Reserved
R-0
7 4 3 2 1 0
Reserved EV_MEM_
EMPTY
EV_BUSY EV_STOP EV_END
R-0 R-1 R-0 R-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 22-34. ADC Event Group Status Register (ADEVSR) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reads return 0. Writes have no effect.
3 EV_MEM_EMPTY Event Group Results Memory Empty. This bit can be effectively used only when the conversion
results are read out of the Event Group results memory in the "read from FIFO" mode.
Any operation mode read:
0 The Event Group results memory has valid conversion results.
1 The Event Group results memory is empty, or does not contain any unread conversion results.
2 EV_BUSY Event Group Conversion Busy.
Any operation mode read:
0 Event Group conversions are neither in progress nor frozen.
1 Event Group conversions are either in progress, or are frozen for servicing some other group.
This bit will always be set when the Event Group is configured to be in the continuous
conversion mode.
1 EV_STOP Event Group Conversion Stopped.
Any operation mode read:
0 Event Group conversions are not currently frozen.
1 Event Group conversions are currently frozen.
0 EV_END Event Group Conversions Ended.
Any operation mode read:
0 Event Group conversions have either not been started or have not yet completed since the last
time this status bit was cleared.
1 The conversion for all the channels selected in the Event Group has completed. This bit can be
cleared under the following conditions:
• By reading a conversion result from the Event Group results memory in the "read from FIFO"
mode.
• By writing a new value to the Event Group channel select register (ADEVSEL).
• By writing a 1 to this bit.
• By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control
register (ADOPMODECR).
To Next Page
Loading...
Need help?
General
