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ADC Registers
925
SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.37 ADC Event Group Results' FIFO Register (ADEVBUFFER)
ADC Event Group Results' FIFO Register (ADEVBUFFER) is shown in Figure 22-60 and Figure 22-61,
and described in Table 22-43. As shown, the format of the data read from the ADEVBUFFER locations is
different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 22-60. 12-bit ADC Event Group Results' FIFO Register (ADEVBUFFER)
[offset = 90h-AFh]
31 30 21 20 16
EV_EMPTY Reserved EV_CHID
R-1 R-0 R-0
15 12 11 0
Reserved EV_DR
R-0 R-U
LEGEND: R = Read only; -n = value after reset; U = value after reset is unknown
Figure 22-61. 10-bit ADC Event Group Results' FIFO Register (ADEVBUFFER)
[offset = 90h-AFh]
31 16
Reserved
R-0
15 14 10 9 0
EV_EMPTY EV_CHID EV_DR
R-1 R-0 R-U
LEGEND: R = Read only; -n = value after reset; U = value after reset is unknown
Table 22-43. ADC Event Group Results' FIFO Register (ADEVBUFFER) Field Descriptions
Field Value Description
Reserved 0 Reads return 0. Writes have no effect.
EV_EMPTY Event Group FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading
the Event Group conversion results.
Any operation mode read:
0 The data in the EV_DR field of this buffer is valid.
1 The data in the EV_DR field of this buffer is not valid and there are no valid data in the Event Group results
memory.
EV_CHID Event Group Channel Id. These bits are also applicable only when the "read from FIFO" mode is used for
reading the Event Group conversion results.
Any operation mode read:
0 The conversion result in the EV_DR field of this buffer is from the ADC input channel 0, or the channel id
mode is disabled in the Event Group mode control register (ADEVMODECR).
1h-1Fh The conversion result in the EV_DR field of this buffer is from the ADC input channel number denoted by
the EV_CHID field.
EV_DR Event Group Digital Conversion Result.
The Event Group results’ FIFO location is aliased eight times, so that any word-aligned read from the
address range 90h to AFh results in one conversion result to be read from the Event Group results’
memory. This allows the ARM LDMIA instruction to read out up to 8 conversion results from the Event
Group results’ memory with just one instruction.
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