Texas Instruments TMS570LC4357 - Page 16

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16
SPNU563A–March 2018
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Contents
22.3.53 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) ........................ 937
22.3.54 ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) ............................. 938
22.3.55 ADC Magnitude Compare Interruptx Mask Register (ADMAGINTxMASK)............................ 940
22.3.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) .................... 941
22.3.57 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR).................. 941
22.3.58 ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG).................................. 942
22.3.59 ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF)................................ 942
22.3.60 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)............................. 943
22.3.61 ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) ................................... 943
22.3.62 ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) ................................... 944
22.3.63 ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) ............................. 944
22.3.64 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR).................................... 945
22.3.65 ADC Group2 RAM Write Address Register (ADG2RAMWRADDR).................................... 945
22.3.66 ADC Parity Control Register (ADPARCR) ................................................................. 946
22.3.67 ADC Parity Error Address Register (ADPARADDR) ..................................................... 947
22.3.68 ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) ....................................... 947
22.3.69 ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) ...... 948
22.3.70 ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) ............ 948
22.3.71 ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL) ............ 949
22.3.72 ADC Event Group Current Count Register (ADEVCURRCOUNT) ..................................... 950
22.3.73 ADC Event Group Maximum Count Register (ADEVMAXCOUNT) .................................... 950
22.3.74 ADC Group1 Current Count Register (ADG1CURRCOUNT) ........................................... 951
22.3.75 ADC Group1 Maximum Count Register (ADG1MAXCOUNT) .......................................... 951
22.3.76 ADC Group2 Current Count Register (ADG2CURRCOUNT) ........................................... 952
22.3.77 ADC Group2 Maximum Count Register (ADG2MAXCOUNT) .......................................... 952
23 High-End Timer (N2HET) Module ........................................................................................ 953
23.1 Overview ................................................................................................................... 954
23.1.1 Features.......................................................................................................... 954
23.1.2 Major Advantages .............................................................................................. 954
23.1.3 Block Diagram................................................................................................... 955
23.1.4 Timer Module Structure and Execution...................................................................... 956
23.1.5 Performance..................................................................................................... 957
23.1.6 N2HET Compared to NHET................................................................................... 957
23.1.7 NHET and N2HET Compared to HET ....................................................................... 957
23.1.8 Instructions Features........................................................................................... 958
23.1.9 Program Usage ................................................................................................. 958
23.2 N2HET Functional Description.......................................................................................... 958
23.2.1 Specialized Timer Micromachine ............................................................................. 958
23.2.2 N2HET RAM Organization .................................................................................... 963
23.2.3 Time Base ....................................................................................................... 966
23.2.4 Host Interface ................................................................................................... 969
23.2.5 I/O Control ....................................................................................................... 970
23.2.6 Suppression Filters ............................................................................................. 986
23.2.7 Interrupts and Exceptions ..................................................................................... 987
23.2.8 Hardware Priority Scheme..................................................................................... 988
23.2.9 N2HET Requests to DMA and HTU.......................................................................... 990
23.3 Angle Functions........................................................................................................... 990
23.3.1 Software Angle Generator..................................................................................... 990
23.3.2 Hardware Angle Generator (HWAG)......................................................................... 995
23.4 N2HET Control Registers .............................................................................................. 1017
23.4.1 Global Configuration Register (HETGCR) ................................................................. 1018
23.4.2 Prescale Factor Register (HETPFR) ....................................................................... 1020
23.4.3 N2HET Current Address Register (HETADDR)........................................................... 1021