0.1
µs
[2 x (13 x 1µs - 0.1µs)]
----------------------------------------------------------
min(TSeg1, TSeg2)
[2 x (13 x bit_time - TSeg2)]
-----------------------------------------------------------------------
CAN Bit Timing
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1424
SPNU563A–March 2018
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Controller Area Network (DCAN) Module
The resulting configuration is written into the Bit Timing Register:
Tseg2 = Phase_Seg2 - 1
Tseg1 = Phase_Seg1 + Prop_Seg - 1
SJW = SynchronizationJumpWidth - 1
BRP = Prescaler - 1
27.3.2.2 Calculation of BRP Values
If Baud and CAN_CLK(VCLK) are already known, the BRP/BRPE values need to be calculated to be
programmed into the register. It is calculated using the following equation:
BRP = CAN_CLK / (BAUD)(1 + TSEG1 + TSEG2) (37)
27.3.2.3 Example for Bit Timing at High Baudrate
In this example, the frequency of CAN_CLK is 10 MHz, BRP is 0, the bit rate is 1 MBit/s.
t
q
100 ns = t
CAN_CLK
delay of bus driver 60 ns
delay of receiver circuit 40 ns
delay of bus line (40m) 220 ns
t
Prop
700 ns = INT (2 × delays + 1) = 7 • t
q
t
SJW
100 ns = 1 × t
q
t
TSeg1
800 ns = t
Prop
+ t
SJW
t
TSeg2
100 ns = Information Processing Time + 1 • t
q
t
Sync-Seg
100 ns = 1 × t
q
bit time 1000 ns = t
Sync-Seg
+ t
TSeg1
+ t
TSeg2
tolerance for CAN_CLK 1.58 % =
(38)
=
(39)
= 0.38%
In this example, the concatenated bit time parameters are (1-1)
3
& (8-1)
4
& (1-1)
2
& (1-1)
6
, so the Bit
Timing Register is programmed to 0000 0700h.
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