Overview
www.ti.com
1498
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.1 Overview
28.1.1 Features
The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (two to 16 bits) to be shifted into and out of the device at a programmed bit-transfer
rate. The MibSPI/SPI is normally used for communication between the microcontroller and external
peripherals or another microcontroller. Typical applications include interface to external I/O or peripheral
expansion via devices such as shift registers, display drivers, and analog-to-digital converters. MibSPI is
an Extension of SPI. MibSPI works in 2 modes.
• Compatibility Mode
• Multi-buffer Mode
The Compatibility mode of MibSPI makes it behave exactly like that of SPI and ensures full compatibility
with the same. Everything described about compatibility mode of MibSPI , in this document, is directly
applicable to SPI.
The Multi-buffer mode of operation is specific to MibSPI alone. This feature is not available in SPI.
The MibSPI supports memory fault detection/correction via internal Parity/ECC circuit. MibSPI is
configurable to include or not include Memory Parity/ECC logic during circuit synthesis.
The SPI / MibSPI can be configured in three pin, four pin or five pin mode of operation. The SPI / MibSPI
allows multiple programmable chip-selects.
The MibSPI has a programmable Multi-buffer array that enables programed transmission to be completed
without CPU intervention. The buffers are combined in different transfer groups that could be triggered by
external events (Timers, I/O, and so on) or by the internal tick counter. The internal tick counter can
support periodic trigger events. Each buffer of the MibSPI can be associated with different DMA channels
in different transfer group, allowing the user to move data from/to internal memory to/from external slave
with a minimal CPU interaction.
The SPICLK, SPISIMO, and SPISOMI pins are used in all MibSPI pin modes. The SPIENA and SPICS
pins are optional and may be used if the pin are present on a given device.
The SPI has the following attributes:
• 16-bit shift register
• Receive buffer register
• 8-bit baud clock generator
• Serial clock (SPICLK) I/O pin
• Up to 8 Slave out, Master in (SPISOMI) I/O pins for faster data transfers
• SPI enable (SPIENA) pin (4 or 5-pin mode only)
• Up to 6 slave chip select (SPICS) pins (4 or 5-pin mode only)
• SPI pins can be used as functional or digital Input/Output pins (GIOs)
The SPI/MibSPI allows software to program the following options:
• SPISOMI/SPISIMO pin direction configuration
• SPICLK pin source (external/internal)
• MibSPI pins as functional or digital I/O pins. For each Buffer, the following features can be selected
from four different combinations of formats using the control fields in the buffer:
– SPICLK frequency
– Character length
– Phase
– Polarity
– Enable/Disable parity for transmit and receive
– Enable/Disable timers for Chip Select Hold and Setup timers
– Direction of shifting, MSBit first or LSBit first
To Next Page
Loading...
Need help?
General
