www.ti.com
Control Registers
1591
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.3.39 Parity/ECC Status Register (PAR_ECC_STAT)
Figure 28-75. Parity/ECC Status Register (PAR_ECC_STAT) [offset = 124]
31 16
Reserved
R-0
15 10 9 8
Reserved SBE_FLG1 SBE_FLG0
R-0 R/W1C-0 R/W1C-0
7 2 1 0
Reserved UERR_ FLG1 UERR_ FLG0
R-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 28-48. Parity/ECC Status Register (PAR_ECC_STAT) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Reads return 0. Writes have no effect.
9 SBE_FLG1 Single-Bit Error in RXRAM. This flag indicates if a single-bit ECC error occurred on reading
RXRAM.
0 Read: No error occurred.
Write: No effect.
1 Read: Single-bit error is detected in RXRAM and the address is captured in SBERRADDR1
register.
Write: Clears the bit.
8 SBE_FLG0 Single-Bit Error in TXRAM. This flag indicates if a single-bit ECC error occurred on reading
TXRAM.
0 Read: No error occurred.
Write: No effect.
1 Read: Single-bit error is detected in TXRAM and the address is captured in SBERRADDR0
register
Write: Clears the bit .
7-2 Reserved 0 Reads return 0. Writes have no effect.
1 UERR_FLG1 Uncorrectable Parity or double-bit ECC error detection flag. This flag indicates if a Parity or
double-bit ECC error occurred on reading RXRAM
0 Read: No error occurred.
Write: No effect.
1 Read: Error detected and the address is captured in UERRADDR1 register.
Write: Clears the bit.
0 UERR_FLG0 Uncorrectable Parity or double-bit ECC error detection flag. This flag indicates if a Parity or
double-bit ECC error occurred on reading TXRAM
0 Read: No error occurred.
Write: No effect.
1 Read: Error detected and the address is captured in UERRADDR0 register.
Write: Clears the bit.
To Next Page
Loading...
Need help?
General
