Control Registers
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SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.3.41 Uncorrectable Parity or Double-Bit ECC Error Address Register - TXRAM
(UERRADDR0)
Figure 28-77. Uncorrectable Parity or Double-Bit ECC Error Address Register - TXRAM
(UERRADDR0) [offset = 12Ch]
31 16
Reserved
R-0
15 11 10 0
Reserved UERRADDR0
R-0 RC-x
LEGEND: R/W = Read/Write; R = Read only; RC = Read to clear; -n = value after reset
Table 28-51. Uncorrectable Parity or Double-Bit ECC Error Address Register - TXRAM
(UERRADDR0) Field Descriptions
Bit Field Value Description
31-11 Reserved 0 Reads return 0. Writes have no effect.
10-0 UERRADDR0 Uncorrectable Parity or double-bit ECC error address. This register holds the address when a
parity error is generated while reading the MibSPI (Transmit) TXRAM. The TXRAM can be read
either by CPU or by the MibSPI Sequencer FSM logic for transmission. The address captured is
byte aligned. This error address is frozen from being updated until it is read by the VBUSP host.
Reading this register clears its contents to the default value of 000. Writes to this register are
ignored.
NOTE: UERRADDR0 values
The offset address of TXRAM can vary from 200h-3FFh, if EXTENDED_BUF mode is
disabled. If the EXTENDED_BUF mode is enabled, the offset address can vary from 400h-
7FFh.
The register does not clear its contents during and after any of the module-level resets, System-level
resets, or even Power-on Reset.
NOTE: A Read to UERRADDR0 register will clear the UERR_FLG0 in PAR_ECC_STAT register.
However, in emulation mode (VBUSP_EMUDBG = 1), the read to UERRADDR0 register
does not clear the corresponding UERR_FLG0.
After a power-on reset the contents will be unpredictable. A read operation can be performed after power-
up to keep the register at its default value if required. Contents of this register are meaningful only when
UERR_FLG0 is set to 1.
If ECC feature is implemented, the Sequencer FSM clearing the TXFULL flag (after a TXRAM location
read out and written to the shift register for transfer) will trigger read-modify-write operation to the RXRAM.
Similarly, each time FSM reads a TXRAM to transfer it out, the corresponding RXRAM location is also
automatically read to determine the status of the buffer. A double-bit error could be detected during these
FSM read operations and result in error address and flags getting captured.
NOTE: Clearing of UERR status and address registers
After completing a memory test sequence, specifically where parity or ECC features are
tested, user must read back the status flags in PAR_ECC_STAT and UERRADDRx registers
and ensure that they are in normal clear state by reading/writing appropriately. This can be
performed before the start of a normal multi-buffer mode transactions as well.
If RAM Parity Check is supported, UERRADDR0[1:0] values will reflect the byte positions of failed byte
based on the following scheme to take care of Endianness of memory organization.
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