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Control Registers
1597
SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Table 28-54. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions (continued)
Bit Field Value Description
16 CTRL DLENERR Controls inducing of the data length error during I/O loopback test mode.
0 Do not cause a data-length error.
1 Induce a data-length error.
Master mode: The SPIENA pin (if functional) is forced to 1 when the module starts
shifting data.
Slave mode: The incoming SPICS pin (if functional) is forced to 1 when the module
starts shifting data.
15-12 Reserved 0 Reads return 0. Writes have no effect.
11-8 IOLPBKSTENA Module I/O loopback test enable key.
Ah Enable I/O loopback test mode.
All Other Values Disable I/O loopback test mode.
7-6 Reserved 0 Reads return 0. Writes have no effect.
5-3 ERR SCS PIN Inject error on chip-select pin number x. The value in this field is decoded as the
number of the chip select pin on which to inject an error. During analog loopback, if
CTRL SCS PIN ERR bit is set to 1, then the chip select pin selected by this field is
forced to the opposite of its value in the CSNR.
0 Select SPICS[0] for injecting error.
1h Select SPICS[1] for injecting error.
: :
7h Select SPICS[7] for injecting error.
2 CTRL SCS PINERR Enable the injection of an error on the SPICS pins. The individual SPICS pins can be
chosen using the ERR SCS PIN field.
0 Disable the SPICS error-inducing logic.
1 Enable the SPICS error-inducing logic.
1 LPBK TYPE Module I/O loopback type (analog/digital). See Figure 28-31 for the different types of
loopback modes.
0 Enable Digital loopback when IOLPBKTSTENA = 1010.
1 Enable Analog loopback when IOLPBKTSTENA = 1010.
0 RXP ENA Enable analog loopback through the receive pin.
Note: This bit is valid only when LPBK TYPE = 1, which chooses analog
loopback mode.
0 Analog loopback is through the transmit pin.
1 Analog loopback is through the receive pin.
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