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Control Registers
1599
SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Table 28-55. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions (continued)
Bit Field Value Description
10-0 EPRESCALE_FMT0 0-7FFh EPRESCALE_FMT0. Extended Prescale value for SPIFMT0. EPRESCALE_FMT0
determines the bit transfer rate of data format 0 if the SPI/MibSPI is the network
master. EPRESCALE_FMT0 is use to derive SPICLK from VCLK. If the SPI is
configured as slave, EPRESCALE_FMT0 does not need to be configured. These
EPRESCALE_FMT0(7:0) bits and PRESCALE0 bits of SPIFMT0 register will point to
the same physically implemented register. The clock rate for data format 0 can be
calculated as:
BR
Format0
= VCLK / (EPRESCALE_FMT0 + 1)
Write: This register field should be written if a SPICLK prescaler of more VCLK/256 is
required. This field provides a prescaler of up to VCLK/2048 for SPICLK. Writing to this
register field will also get reflected in SPIFMT0(15:8).
Read: Reading this field will reflect the PRESCALE value based on the last written
register field, that is, EXTENDED_PRESCALE0(10:0) or SPIFMT0(15:8) register.
Note: If Extended Prescaler is required, it should be ensured that
EXTENDED_PRESCALE1 register is programmed after SPIFMT0 register is
programmed. This is to ensure that the final SPICLK prescale value is controlled
by EXTENDED_PRESCALE1 register when a prescale of more 256 is intended on
SPICLK. Writing to PRESCALE0 field of SPIFMT0 will automatically clear
EPRESCALE_FMT0(10:8) bits to 000 so that the integrity of PRESCALE value is
maintained.
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