Introduction and Features
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SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.1.3 Block Diagram
The SCI/LIN module contains core SCI block with added sub-blocks to support LIN protocol.
Three Major components of the SCI Module are:
• Transmitter
• Baud Clock Generator
• Receiver
Transmitter (TX) contains two major registers to perform the double- buffering:
• The transmitter data buffer register (SCITD) contains data loaded by the CPU to be transferred to the
shift register for transmission.
• The transmitter shift register (SCITXSHF) loads data from the data buffer (SCITD) and shifts data onto
the LINTX pin, one bit at a time.
Baud Clock Generator
• A programmable baud generator produces either a baud clock scaled from VBUSP CLK.
Receiver (RX) contains two major registers to perform the double- buffering:
• The receiver shift register (SCIRXSHF) shifts data in from the LINRX pin one bit at a time and transfers
completed data into the receive data buffer.
• The receiver data buffer register (SCIRD) contains received data transferred from the receiver shift
register
The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt
bits. The receiver and transmitter may each be operated independently or simultaneously in full duplex
mode.
To ensure data integrity, the SCI checks the data it receives for breaks, parity, overrun, and framing
errors. The bit rate (baud) is programmable to over 16 million different rates through a 24-bit baud-select
register. Figure 29-1 shows the detailed SCI block diagram.
The SCI/LIN module is based on the standalone SCI with the addition of an error detector (parity
calculator, checksum calculator, and bit monitor), a mask filter, a synchronizer, and a multi-buffered
receiver and transmitter. The SCI interface, the DMA control subblocks and the baud generator are
modified as part of the hardware enhancements for LIN compatibility. Figure 29-2 shows the SCI/LIN
block diagram.
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