LIN
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SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.3.1.10 Receive Buffers
To reduce CPU load when receiving a LIN N-byte (with N = 1–8) response in interrupt mode or DMA
mode, the SCI/LIN module has eight receive buffers. These buffers can store an entire LIN response in
the RDy receive buffers. Figure 29-8 illustrates the receive buffers.
The checksum byte following the data bytes is validated by the internal checksum calculator. The
checksum error (CE) flag indicates a checksum error and a CE interrupt will be generated if enabled in the
SCISETINT register.
The multi-buffer 3-bit counter counts the data bytes transferred from the SCIRXSHF register to the RDy
receive buffers if multi-buffer mode is enabled, or to RD0 if multi-buffer mode is disabled. The 3-bit
compare register contains the number of data bytes expected to be received. In cases where the ID BYTE
field does not convey message length (see Note:Optional Control Length Bits in Section 29.3.1.5), the
LENGTH value, indicates the expected length and is used to load the 3-bit compare register. Whether the
length control field or the LENGTH value is used is selectable with the COMM MODE bit.
A receive interrupt, and a receive ready RXRDY flag set as well as a DMA request (RXDMA) could occur
after receiving a response if there are no response receive errors for the frame (such as, there is no
checksum error, frame error, and overrun error). The checksum byte will be compared before
acknowledging a reception. A DMA request can be generated for each received byte or for the entire
response depending on whether the multi-buffer mode is enabled or not (MBUF MODE bit).
NOTE: In multi-buffer mode following are the scenarios associated with clearing the "RXRDY" flag
bit:
1. The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0/1 register.
2. For LENGTH less than or equal to 4, Read to RD0 register will clear the “RXRDY” flag.
3. For LENGTH greater than 4, Read to RD1 register will clear the “RXRDY” flag.
29.3.1.11 Transmit Buffers
To reduce the CPU load when transmitting a LIN N-byte (with N = 1–8) response in interrupt mode or
DMA mode, the SCI/LIN module has eight transmit buffers, TD0–TD7 in LINTD0 and LINTD1. With these
transmit buffers, an entire LIN response field can be preloaded in the TXy transmit buffers. Optionally, a
DMA transfer could be done on a byte-per-byte basis when multi-buffer mode is not enabled (MBUF
MODE bit). Figure 29-9 illustrates the transmit buffers.
The multi-buffer 3-bit counter counts the data bytes transferred from the TDy transmit buffers register if
multi-buffer mode is enabled, or from TD0 to SCITXSHF if multi-buffer mode is disabled. The 3-bit
compare register contains the number of data bytes expected to be transmitted. If the ID field is not used
to convey message length (see Note:Optional Control Length Bits in Section 29.3.1.5), the LENGTH value
indicates the expected length and is used instead to load the 3-bit compare register. Whether the length
control field or the LENGTH value is used is selectable with the COMM MODE bit.
A transmit interrupt (TX interrupt), and a transmit ready flag (TXRDY flag), and a DMA request (TXDMA)
could occur after transmitting a response. A DMA request can be generated for each transmitted byte or
for the entire response depending on whether multi-buffer mode is enabled or not (MBUF MODE bit).
The checksum byte will be automatically generated by the checksum calculator and sent after the data-
fields transmission is finished. The multi-buffer 3-bit counter counts the data bytes transferred from the
TDy buffers into the SCITXSHF register.
NOTE: The transmit interrupt request can be eliminated until the next series of data is written into
the transmit buffers LINTD0 and LINTD1, by disabling the corresponding interrupt via the
SCICLRINT register or by disabling the transmitter via the TXENA bit.
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