Texas Instruments TMS570LC4357

eCAP Registers www.ti.com
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SPNU563A–March 2018
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Enhanced Capture (eCAP) Module
33.5.10 ECAP Interrupt Enable Register (ECEINT)
The interrupt enable bits block any of the selected events from generating an interrupt. Events will still be
latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers.
The proper procedure for configuring peripheral modes and interrupts is as follows:
• Disable global interrupts
• Stop eCAP counter
• Disable eCAP interrupts
• Configure peripheral registers
• Clear spurious eCAP interrupt flags
• Enable eCAP interrupts
• Start eCAP counter
• Enable global interrupts
Figure 33-23. ECAP Interrupt Enable Register (ECEINT) [offset = 2Eh]
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
CTR_CMP CTR_PRD CTROVF CEVT4 CEVT3 CEVT2 CETV1 Reserved
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33-11. ECAP Interrupt Enable Register (ECEINT) Field Descriptions
Bits Field Value Description
15-8 Reserved 0 Reserved
7 CTR_CMP Counter Equal Compare Interrupt Enable.
0 Disable Compare Equal as an Interrupt source.
1 Enable Compare Equal as an Interrupt source.
6 CTR_PRD Counter Equal Period Interrupt Enable.
0 Disable Period Equal as an Interrupt source.
1 Enable Period Equal as an Interrupt source.
5 CTROVF Counter Overflow Interrupt Enable.
0 Disabled counter Overflow as an Interrupt source.
1 Enable counter Overflow as an Interrupt source.
4 CEVT4 Capture Event 4 Interrupt Enable.
0 Disable Capture Event 4 as an Interrupt source.
1 Capture Event 4 Interrupt Enable.
3 CEVT3 Capture Event 3 Interrupt Enable.
0 Disable Capture Event 3 as an Interrupt source.
1 Enable Capture Event 3 as an Interrupt source.
2 CEVT2 Capture Event 2 Interrupt Enable.
0 Disable Capture Event 2 as an Interrupt source.
1 Enable Capture Event 2 as an Interrupt source.
1 CEVT1 Capture Event 1 Interrupt Enable.
0 Disable Capture Event 1 as an Interrupt source.
1 Enable Capture Event 1 as an Interrupt source.
0 Reserved 0 Reserved