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eQEP Registers
1985
SPNU563A–March 2018
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Enhanced Quadrature Encoder Pulse (eQEP) Module
34.3.13 eQEP Decoder Control Register (QDECCTL)
Figure 34-33. eQEP Decoder Control Register (QDECCTL) [offset = 2Ah]
15 14 13 12 11 10 9 8
QSRC SOEN SPSEL XCR SWAP IGATE QAP
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 0
QBP QIP QSP Reserved
R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-16. eQEP Decoder Control Register (QDECCTL) Field Descriptions
Bits Name Value Description
15-14 QSRC Position-counter source selection.
0 Quadrature count mode: (QCLK = iCLK, QDIR = iDIR).
1h Direction-count mode: (QCLK = xCLK, QDIR = xDIR).
2h UP count mode for frequency measurement :(QCLK = xCLK, QDIR = 1).
3h DOWN count mode for frequency measurement: (QCLK = xCLK, QDIR = 0).
13 SOEN Sync output-enable.
0 Position-compare sync output is disabled.
1 Position-compare sync output is enabled.
12 SPSEL Sync output pin selection.
0 Index pin is used for sync output.
1 Strobe pin is used for sync output.
11 XCR External clock rate.
0 2x resolution: Count the rising/falling edge.
1 1x resolution: Count the rising edge only.
10 SWAP Swap quadrature clock inputs. This swaps the input to the quadrature decoder, reversing the
counting direction.
0 Quadrature-clock inputs are not swapped.
1 Quadrature-clock inputs are swapped.
9 IGATE Index pulse gating option.
0 Disable gating of Index pulse.
1 Gate the index pin with strobe.
8 QAP QEPA input polarity.
0 No effect.
1 Negates QEPA input.
7 QBP QEPB input polarity.
0 No effect.
1 Negates QEPB input.
6 QIP QEPI input polarity.
0 No effect.
1 Negates QEPI input.
5 QSP QEPS input polarity.
0 No effect.
1 Negates QEPS input.
4-0 Reserved 0 Always read as 0.