Texas Instruments TMS570LC4357

ePWM Registers www.ti.com
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SPNU563A–March 2018
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Enhanced Pulse Width Modulator (ePWM) Module
35.4.1.2 Time-Base Control Register (TBCTL)
Figure 35-64. Time-Base Control Register (TBCTL) [offset = 02h]
15 14 13 12 10 9 8
FREE SOFT PHSDIR CLKDIV HSPCLKDIV
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
HSPCLKDIV SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-3h
LEGEND: R/W = Read/Write; -n = value after reset
Table 35-24. Time-Base Control Register (TBCTL) Field Descriptions
Bit Field Value Description
15-14 FREE, SOFT Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
emulation events:
0 Stop after the next time-base counter increment or decrement.
1h Stop when counter completes a whole cycle:
• Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)
• Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
• Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
2h-3h Free run
13 PHSDIR Phase Direction Bit.
This bit is only used when the time-base counter is configured in the up-down-count mode. The
PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization
event occurs and a new phase value is loaded from the phase (TBPHS) register. This is
irrespective of the direction of the counter before the synchronization event..
In the up-count and down-count modes this bit is ignored.
0 Count down after the synchronization event.
1 Count up after the synchronization event.
12-10 CLKDIV Time-base Clock Prescale Bits.
These bits determine part of the time-base clock prescale value:
TBCLK = VCLK3 / (HSPCLKDIV × CLKDIV)
0 /1 (default on reset)
1h /2
2h /4
3h /8
4h /16
5h /32
6h /64
7h /128
9-7 HSPCLKDIV High Speed Time-base Clock Prescale Bits.
These bits determine part of the time-base clock prescale value:
TBCLK = VCLK3 / (HSPCLKDIV × CLKDIV)
0 /1
1h /2 (default on reset)
2h /4
3h /6
4h /8
5h /10
6h /12
7h /14