Texas Instruments TMS570LC4357

ePWM Registers www.ti.com
2090
SPNU563A–March 2018
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Enhanced Pulse Width Modulator (ePWM) Module
35.4.5.5 Trip-Zone Clear Register (TZCLR)
Figure 35-82. Trip-Zone Clear Register (TZCLR) [offset = 2Ch]
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved DCBEVT2 DCBEVT1 DCAEVT2 DCAEVT1 OST CBC INT
R-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 35-42. Trip-Zone Clear Register (TZCLR) Field Descriptions
Bit Field Value Description
15-7 Reserved 0 Reserved
6 DCBEVT2 Clear Flag for Digital Compare Output B Event 2.
0 Writing 0 has no effect. This bit always reads back 0.
1 Writing 1 clears the DCBEVT2 event trip condition.
5 DCBEVT1 Clear Flag for Digital Compare Output B Event 1.
0 Writing 0 has no effect. This bit always reads back 0.
1 Writing 1 clears the DCBEVT1 event trip condition.
4 DCAEVT2 Clear Flag for Digital Compare Output A Event 2.
0 Writing 0 has no effect. This bit always reads back 0.
1 Writing 1 clears the DCAEVT2 event trip condition.
3 DCAEVT1 Clear Flag for Digital Compare Output A Event 1.
0 Writing 0 has no effect. This bit always reads back 0.
1 Writing 1 clears the DCAEVT1 event trip condition.
2 OST Clear Flag for One-Shot Trip (OST) Latch.
0 Has no effect. Always reads back a 0.
1 Clears this Trip (set) condition.
1 CBC Clear Flag for Cycle-By-Cycle (CBC) Trip Latch.
0 Has no effect. Always reads back a 0.
1 Clears this Trip (set) condition.
0 INT Global Interrupt Clear Flag.
0 Has no effect. Always reads back a 0.
1 Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).
NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the
TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt pulse will be
generated. Clearing all flag bits will prevent further interrupts.