Texas Instruments TMS570LC4357

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SPNU563A–March 2018
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Data Modification Module (DMM)
36.3.21 DMM Pin Control 5 (DMMPC5)
This register allows to set individual pins to a logic low level without having to do a read-modify-write
operation as would be the case with the DMMPC3 register (Section 36.3.19). Writing a one to a bit will
change the output to a logic low level, writing a zero will not change the state of the pin.
Figure 36-27. DMM Pin Control 5 (DMMPC5) [offset = 80h]
31 24
Reserved
R-0
23 19 18 17 16
Reserved ENACLR DATA15CLR DATA14CLR
R-0 R/WP-0 R/WP-0 R/WP-0
15 14 13 12 11 10 9 8
DATA13CLR DATA12CLR DATA11CLR DATA10CLR DATA9CLR DATA8CLR DATA7CLR DATA6CLR
R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
7 6 5 4 3 2 1 0
DATA5CLR DATA4CLR DATA3CLR DATA2CLR DATA1CLR DATA0CLR CLKCLR SYNCCLR
R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 36-27. DMM Pin Control 5 (DMMPC5) Field Descriptions
Bit Field Value Description
31-19 Reserved 0 Reads returns 0. Writes have no effect.
18 ENACLR Sets output state of DMMENA pin to logic low. Value in the ENACLR bit clears the data output
control register bit to 0, regardless of the current value in the ENAOUT bit.
User and privilege mode (read):
0 Logic low (output voltage is V
OL
or lower).
1 Logic high (output voltage is V
OH
or higher).
Privilege mode (write):
0 State of the pin is unchanged.
1 Clears the pin to logic low (output voltage is set to V
OL
or lower).
17-2 DATAxCLR Sets output state of DMMDATA[x] pin to logic low. Value in the DATAxCLR bit clears the data
output control register DATAxOUT bit to 0, regardless of the current value in the DATAxOUT bit.
User and privilege mode (read):
0 Logic low (output voltage is V
OL
or lower).
1 Logic high (output voltage is V
OH
or higher).
Privilege mode (write):
0 State of the pin is unchanged.
1 Clears the pin to logic low (output voltage is set to V
OL
or lower).
1 CLKCLR Sets output state of DMMCLK pin to logic low. Value in the CLKCLR bit clears the data output
control register CLKOUT bit to 0, regardless of the current value in the CLKOUT bit.
User and privilege mode (read):
0 Logic low (output voltage is V
OL
or lower).
1 Logic high (output voltage is V
OH
or higher).
Privilege mode (write):
0 State of the pin is unchanged.
1 Clears the pin to logic low (output voltage is set to V
OL
or lower).