Texas Instruments TMS570LC4357

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5
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
7.1.3 F021 Flash Tools ................................................................................................ 340
7.2 Default Flash Configuration ............................................................................................. 340
7.3 EEPROM Emulation Support............................................................................................ 340
7.4 SECDED ................................................................................................................... 341
7.4.1 SECDED Initialization ........................................................................................... 341
7.4.2 ECC Encoding.................................................................................................... 341
7.4.3 Syndrome Table: Decode to Bit in Error...................................................................... 343
7.4.4 Syndrome Table: An Alternate Method ....................................................................... 344
7.5 Memory Map .............................................................................................................. 345
7.5.1 Location of Flash ECC Bits..................................................................................... 345
7.5.2 OTP Memory ..................................................................................................... 346
7.6 Power On, Power Off Considerations.................................................................................. 350
7.6.1 Error Checking at Power On ................................................................................... 350
7.6.2 Flash Integrity at Power Off .................................................................................... 350
7.7 Emulation and SIL3 Diagnostic Modes ................................................................................ 350
7.7.1 System Emulation ............................................................................................... 350
7.7.2 Diagnostic Mode ................................................................................................. 350
7.7.3 Diagnostic Mode Summary..................................................................................... 352
7.7.4 SECDED Software Diagnostic ................................................................................. 353
7.7.5 Read Margin...................................................................................................... 353
7.8 Parameter Overlay Module (POM) ..................................................................................... 353
7.8.1 Example Procedure to Configure the POM .................................................................. 353
7.9 Summary of L2FMC Errors.............................................................................................. 354
7.10 Flash Control Registers.................................................................................................. 355
7.10.1 Flash Read Control Register (FRDCNTL)................................................................... 356
7.10.2 Read Margin Control Register (FSPRD)..................................................................... 357
7.10.3 EEPROM Error Correction Control Register (EE_FEDACCTRL1)....................................... 358
7.10.4 Flash Port A Error and Status Register (FEDAC_PASTATUS) .......................................... 359
7.10.5 Flash Port B Error and Status Register (FEDAC_PBSTATUS) .......................................... 360
7.10.6 Flash Global Error and Status Register (FEDAC_GBLSTATUS) ........................................ 361
7.10.7 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)......................... 362
7.10.8 Primary Address Tag Register (FPRIM_ADD_TAG)....................................................... 363
7.10.9 Duplicate Address Tag Register (FDUP_ADD_TAG)...................................................... 363
7.10.10 Flash Bank Protection Register (FBPROT)................................................................ 364
7.10.11 Flash Bank Sector Enable Register (FBSE)............................................................... 364
7.10.12 Flash Bank Busy Register (FBBUSY) ...................................................................... 365
7.10.13 Flash Bank Access Control Register (FBAC) ............................................................. 365
7.10.14 Flash Bank Power Mode Register (FBPWRMODE) ..................................................... 366
7.10.15 Flash Bank/Pump Ready Register (FBPRDY) ............................................................ 367
7.10.16 Flash Pump Access Control Register 1 (FPAC1)......................................................... 368
7.10.17 Flash Module Access Control Register (FMAC) .......................................................... 369
7.10.18 Flash Module Status Register (FMSTAT).................................................................. 370
7.10.19 EEPROM Emulation Data MSW Register (FEMU_DMSW) ............................................. 372
7.10.20 EEPROM Emulation Data LSW Register (FEMU_DLSW)............................................... 372
7.10.21 EEPROM Emulation ECC Register (FEMU_ECC) ....................................................... 373
7.10.22 Flash Lock Register (FLOCK) ............................................................................... 373
7.10.23 Diagnostic Control Register (FDIAGCTRL)................................................................ 374
7.10.24 Raw Address Register (FRAW_ADDR) ................................................................... 375
7.10.25 Parity Override Register (FPAR_OVR)..................................................................... 376
7.10.26 Reset Configuration Valid Register (RCR_VALID) ....................................................... 377
7.10.27 Crossbar Access Time Threshold Register (ACC_THRESHOLD) ..................................... 377
7.10.28 Flash Error Detection and Correction Sector Disable Register 2 (FEDACSDIS2) ................... 378
7.10.29 Lower Word of Reset Configuration Read Register (RCR_VALUE0).................................. 379