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SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
7.10.30 Upper Word of Reset Configuration Read Register (RCR_VALUE1).................................. 379
7.10.31 FSM Register Write Enable Register (FSM_WR_ENA).................................................. 380
7.10.32 EEPROM Emulation Configuration Register (EEPROM_CONFIG) .................................... 380
7.10.33 FSM Sector Register 1 (FSM_SECTOR1)................................................................. 381
7.10.34 FSM Sector Register 2 (FSM_SECTOR2)................................................................. 381
7.10.35 Flash Bank Configuration Register (FCFG_BANK)....................................................... 382
7.11 POM Control Registers .................................................................................................. 383
7.11.1 POM Global Control Register (POMGLBCTRL)............................................................ 383
7.11.2 POM Revision ID Register (POMREV) ...................................................................... 384
7.11.3 POM Flag Register (POMFLG) ............................................................................... 384
7.11.4 POM Region Start Address Register (POMPROGSTARTx).............................................. 385
7.11.5 POM Overlay Region Start Address Register (POMOVLSTARTx) ...................................... 385
7.11.6 POM Region Size Register (POMREGSIZEx).............................................................. 386
8 Level 2 RAM (L2RAMW) Module ......................................................................................... 387
8.1 Overview ................................................................................................................... 388
8.2 Module Operation......................................................................................................... 388
8.2.1 RAM Memory Map............................................................................................... 388
8.2.2 Safety Features .................................................................................................. 389
8.2.3 L2RAMW Auto-Initialization .................................................................................... 392
8.2.4 Trace Module Support .......................................................................................... 392
8.2.5 Emulation/Debug Mode Behavior.............................................................................. 392
8.2.6 Diagnostic Test Procedure ..................................................................................... 392
8.3 Control and Status Registers............................................................................................ 393
8.3.1 L2RAMW Module Control Register (RAMCTRL) ............................................................ 393
8.3.2 L2RAMW Error Status Register (RAMERRSTATUS)....................................................... 395
8.3.3 L2RAMW Diagnostic Data Vector High Register (DIAG_DATA_VECTOR_H).......................... 398
8.3.4 L2RAMW Diagnostic Data Vector Low Register (DIAG_DATA_VECTOR_L)........................... 398
8.3.5 L2RAMW Diagnostic ECC Vector Register (DIAG_ECC).................................................. 399
8.3.6 L2RAMW RAM Test Mode Control Register (RAMTEST) ................................................. 400
8.3.7 L2RAMW RAM Address Decode Vector Test Register (RAMADDRDEC_VECT)...................... 401
8.3.8 L2RAMW Memory Initialization Domain Register (MEMINIT_DOMAIN) ................................. 402
8.3.9 L2RAMW Bank to Domain Mapping Register0 (BANK_DOMAIN_MAP0) ............................... 403
8.3.10 L2RAMW Bank to Domain Mapping Register1 (BANK_DOMAIN_MAP1).............................. 404
9 Programmable Built-In Self-Test (PBIST) Module.................................................................. 405
9.1 Overview ................................................................................................................... 406
9.1.1 Features of PBIST............................................................................................... 406
9.1.2 PBIST vs. Application Software-Based Testing.............................................................. 406
9.1.3 PBIST Block Diagram ........................................................................................... 406
9.2 RAM Grouping and Algorithm........................................................................................... 407
9.3 PBIST Flow................................................................................................................ 408
9.3.1 PBIST Sequence................................................................................................. 409
9.4 Memory Test Algorithms on the On-chip ROM ...................................................................... 411
9.5 PBIST Control Registers ................................................................................................ 412
9.5.1 RAM Configuration Register (RAMT) ......................................................................... 413
9.5.2 Datalogger Register (DLR) ..................................................................................... 414
9.5.3 PBIST Activate/Clock Enable Register (PACT).............................................................. 415
9.5.4 PBIST ID Register ............................................................................................... 416
9.5.5 Override Register (OVER)...................................................................................... 417
9.5.6 Fail Status Fail Register (FSRF0) ............................................................................. 418
9.5.7 Fail Status Count Registers (FSRC0 and FSRC1).......................................................... 419
9.5.8 Fail Status Address Registers (FSRA0 and FSRA1) ....................................................... 420
9.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1) ........................................................ 421
9.5.10 ROM Mask Register (ROM)................................................................................... 422
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