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SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
9.5.11 ROM Algorithm Mask Register (ALGO) ..................................................................... 423
9.5.12 RAM Info Mask Lower Register (RINFOL) .................................................................. 424
9.5.13 RAM Info Mask Upper Register (RINFOU).................................................................. 425
9.6 PBIST Configuration Example .......................................................................................... 426
9.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM..................... 426
9.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups ................ 427
10 Self-Test Controller (STC) Module....................................................................................... 428
10.1 General Description ...................................................................................................... 429
10.1.1 Self-Test Controller Features ................................................................................. 429
10.1.2 Terminology ..................................................................................................... 430
10.1.3 STC Block Diagram ............................................................................................ 430
10.2 STC Module Assignments............................................................................................... 436
10.3 STC Programmers Flow ................................................................................................. 437
10.4 Application Self-Test Flow............................................................................................... 438
10.4.1 STC Module Configuration .................................................................................... 438
10.4.2 Context Saving - CPU.......................................................................................... 438
10.4.3 Entering CPU Idle Mode....................................................................................... 439
10.4.4 Entering nHET Idle Mode...................................................................................... 439
10.4.5 Self-Test Completion and Error Generation................................................................. 439
10.5 STC1 Segment 0 (CPU) Test Coverage and Duration .............................................................. 441
10.6 STC1 Segment 1 (µSCU) Test Coverage and Duration............................................................. 444
10.7 STC2 (nHET) Test Coverage and Duration ........................................................................... 444
10.8 STC Control Registers ................................................................................................... 446
10.8.1 STC Global Control Register 0 (STCGCR0) ................................................................ 447
10.8.2 STC Global Control Register 1 (STCGCR1) ................................................................ 448
10.8.3 Self-Test Run Timeout Counter Preload Register (STCTPR) ............................................ 449
10.8.4 STC Current ROM Address Register - CORE1 (STCCADDR1) ......................................... 450
10.8.5 STC Current Interval Count Register (STCCICR).......................................................... 450
10.8.6 Self-Test Global Status Register (STCGSTAT) ............................................................ 451
10.8.7 Self-Test Fail Status Register (STCFSTAT) ................................................................ 452
10.8.8 CORE1 Current MISR Registers (CORE1_CURMISR[3:0]) .............................................. 453
10.8.9 CORE2 Current MISR Registers (CORE2_CURMISR[3:0]) .............................................. 454
10.8.10 Signature Compare Self-Check Register (STCSCSCR)................................................. 455
10.8.11 STC Current ROM Address Register - CORE2 (STCCADDR2)........................................ 455
10.8.12 STC Clock Prescalar Register (STCCLKDIV)............................................................. 456
10.8.13 Segment Interval Preload Register (STCSEGPLR) ...................................................... 457
10.9 STC Configuration Example............................................................................................. 458
10.9.1 Example: STC1 Self-Test Run................................................................................ 458
10.10 Self-Test Controller Diagnostics........................................................................................ 459
11 System Memory Protection Unit (NMPU).............................................................................. 460
11.1 Overview ................................................................................................................... 461
11.1.1 Features.......................................................................................................... 461
11.1.2 Safety Diagnostic ............................................................................................... 461
11.1.3 Block Diagram................................................................................................... 462
11.2 Module Operation......................................................................................................... 463
11.2.1 Functional Mode ................................................................................................ 463
11.2.2 Diagnostic Mode ................................................................................................ 465
11.2.3 Functional Fail Safe ............................................................................................ 465
11.3 How to Use NMPU ....................................................................................................... 466
11.3.1 How to Use NMPU in Functional Mode...................................................................... 466
11.3.2 How to Use Diagnostics ....................................................................................... 468
11.4 NMPU Registers .......................................................................................................... 471
11.4.1 MPU Revision ID Register (MPUREV)....................................................................... 472
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